Manufacturing process for ultra slim electrooptic display device unit

ABSTRACT

To obtain a high intensity, high definition and sophisticated electrooptic display device unit such as LCD or EL, which has high electron and positive hole mobility and low leak electric current qualities.  
     A porous semiconductor layer, a monocrystalline Si layer, and a SiO 2  layer are formed on a monocrystalline Si substrate. The SiO 2  layer of the peripheral circuit area is removed, leaving the SiO 2  layer in the display area. A poly Si layer is formed in the display area by epitaxial growth, and a monocrystalline Si layer is formed in the peripheral circuit area. Then, the display element section is formed in the display area and the peripheral circuitry section is formed in the peripheral circuit area. The assembly is then divided and packaged into ultra slim electrooptic display device units.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the manufacturing process for ultra slimelectrooptic display device units such as high intensity, highdefinition and sophisticated transmissive liquid crystal display deviceunits (LCD; Liquid Crystal Display), semi-transmissive liquid crystaldisplay device units, highly reflective liquid crystal display deviceunits, top surface luminous organic EL (Electro Luminescence) displaydevice units and under surface luminous organic EL display device units.

2. Description of Related Art

In the case of a transmissive, high temperature polycrystalline silicon(which we will call “Poly-Si” from here on) TFT (thin Film Transistor)LCD, a micro crystal Si thin film is formed by decreased pressure CVD(Chemical Vapor Deposition), etc. on quartz glass. After converting toamorphic Si, a large particle diameter poly Si thin film is formed byion implantation using the solid phase deposition method, for example ata temperature of 620° C. for 12 hours and the LCD peripheral circuitryand the display element, etc. will be formed on the film.

In the case of transmitted or reflective low temperature Poly-SiTFT LCDor organic EL (Electro Luminescence) displays (which we will call“Organic EL” from here on), an amorphous Si thin film is formed on a lowstrain point glass such as borosilicate glass or aluminosilicate glassby plasma CVD, etc. Then a large particle diameter Poly-Si thin filmwill be formed via crystallization by excimer laser anneal (ELA) and theLCD peripheral circuitry and display element, or the organic ELperipheral circuitry and the display elements, etc. are formed on thefilm.

However, in the case of the high temperature Poly-SiTFT LCD, the lowtemperature Poly-SiTFT LCD or the organic EL, the LCD or organic ELperipheral circuitry is formed on the Poly-Si thin film where the highelectron and positive hole mobility is not high in comparison withmonocrystalline Si. Because of this, the device quality and especiallyhigh speed operational characteristics become a problem.

In recent years, a LCOS (Liquid Crystal On Silicon) also calledreflective LCD has been adopted for projectors, etc. This is a result ofutilizing the high electron and positive hole mobility ofmonocrystalline Si. The LCOS which utilizes general purpose MOSLSItechnology, works with not only the peripheral circuitry and the displayelement on a monocrystalline Si substrate surface but also withfunctions such as video signal process circuitry and memory circuitry,etc. It has characteristics such as high intensity, high definition andadvanced functionality.

However, with LCOS, it is easy to have problems with picture quality andwith reliability resulting from TFT leak electric current due to strongincident light. As a result, there is an increase in manufacturingman-hours, and a yield and production decrease due to the light leakageissue. Although we can think of adopting a SOI (Silicon on Insulator)substrate (for instance, please see the patent document 1˜6) amonocrystalline Si substrate does not achieve optical transparency inthis case. It is limited to a reflective LCD and an upper surfaceluminous organic EL.

This inventor has proposed a method of producing a transmissive LCDusing a monocrystalline Si substrate in patent document 7. In this case,the transmissive LCD is formed by embedding the image display elementswhich have internal peripheral circuitry and a reflective film on amonocrystalline Si substrate surface in a transparent resin. By grindingand polishing the other side, a monocrystalline Si thin film matrixarray is formed, to which a color filter substrate is attached withtransparent resin.

(Patent Document 1) Patent #2608351 Official Bulletin

(Patent Document 2) Open Patent Tokukaihei #11-195562 Official Bulletin

(Patent Document 3) Patent #3048201 Official Bulletin

(Patent Document 4) Open Patent Tokukai #2000-196047 Official Bulletin

(Patent Document 5) Open Patent Tokukai #2001-77044 Official Bulletin

(Patent Document 6) Open Patent Tokukaihei #5-211128 Official Bulletin

(Patent Document 7) Patent #3218861 Official Bulletin

(Open Disclosure for the Patent)

However, in case where a transmissive LCD which is composed of theperipheral circuitry and the image element display on the surface of amonocrystalline Si substrate such as described in the patent document 7is used in a unit such as a projector that reflects strong light, themonocrystalline Si substrate has high electron and positive holemobility and very high sensitivity which causes a problem with TFTcurrent leakage when exposed to strong incident light.

Even with a high intensity reflective LCD such as recent LCOS types, aproblem with TFT current leakage of the display caused by strongincident radiation can be a problem. In the future, it is still possibleto have a problem with TFT current leakage as a result of internallygenerated light as the intensity strengthens even with an under surfaceluminous organic EL.

SUMMARY OF THE INVENTION

The purpose of this invention is to create a high intensity, highdefinition and sophisticated electrooptic display device unit such as atransmissive LCD, a reflective LCD, a semi-transmissive LCD, an uppersurface luminous organic EL or an upper surface luminous organic EL thathas a low current leakage attribute and high electron and positive holemobility.

The manufacturing process for the first ultra slim electrooptic displaydevice unit in this invention includes the following: a process to forma porous semiconductor layer on a supporting substrate which consists ofa monocrystalline semiconductor, a process to form a monocrystallinesemiconductor layer via a porous semiconductor layer on a supportingsubstrate, processes to form a polycrystalline semiconductor layer inthe display area by semiconductor epitaxial growth and a monocrystallinesemiconductor layer in the peripheral circuitry area by forming aninsulating layer on the surface of the monocrystalline semiconductorlayer and removing an insulating layer in the peripheral circuitry andleaving an insulating layer in a display area, processes to form thedisplay elements in a polycrystalline semiconductor layer in the displayarea and the peripheral circuitry in a monocrystalline semiconductorlayer in the peripheral circuitry area, a process to separate thesupporting substrate from the porous semiconductor layer, a process toattach a backing to an ultra slim electrooptic display element substrateafter the separation and a process to divide each ultra slimelectrooptic display device unit after attaching the backings.

In this manufacturing method, a porous semiconductor layer and amonocrystalline semiconductor layer are formed on a supporting substratewhich consists of a monocrystalline semiconductor. An insulating layeris formed on this monocrystalline semiconductor layer. An insulatinglayer in the peripheral circuitry area is removed while an insulatinglayer is left in a display area. This forms a polycrystallinesemiconductor layer in the display area and a monocrystallinesemiconductor layer in the peripheral circuitry. Using semiconductorepitaxial growth, display elements are formed on a polycrystallinesemiconductor layer in the display area and peripheral circuitry isformed on a monocrystalline semiconductor layer in the peripheralcircuitry area. As a result, a polycrystalline semiconductor TFT displayelement that has comparatively low high electron and positive holemobility and low current leakage attributes, and monocrystallinesemiconductor TFT peripheral circuitry that has high electron andpositive hole mobility and high drivability can be formed on the samesupporting substrate. And by dividing the assembly into each individualultra slim electrooptic display device units after separating thesupporting substrate from the porous semiconductor layer by attachingthe backing, you can obtain a high intensity, high definition andsophisticated ultra slim electrooptic display device unit that has highelectron and positive hole mobility and low current leakage attributes.

The manufacturing process for the second ultra slim electrooptic displaydevice unit in this invention includes as follows: a process to form aporous semiconductor layer on both a seed substrate and a supportsubstrate where each is comprised of monocrystalline semiconductor, aprocess to form a monocrystalline semiconductor layer through a poroussemiconductor layer on both a seed substrate and a support substrate, aprocess to form an insulating layer through a monocrystallinesemiconductor layer on either the seed substrate or a supportingsubstrate, a process to attach a seed substrate to a supportingsubstrate to form a surface insulating layer, a process to separate aseed substrate from a porous semiconductor layer of a seed substrate, aplanarization process on a monocrystalline semiconductor layer surfacethat was exposed by separation of a seed substrate by etching it with aminimum hydrogen anneal treatment, a process to form both amonocrystalline semiconductor layer in the peripheral circuitry area andpolycrystalline semiconductor layer in the display area by semiconductorepitaxial growth via forming an insulating layer on a monocrystallinesemiconductor layer surface and removing the insulating layer in theperipheral circuitry area which is done by etching while leaving theinsulating layer in the display area, a process to form both displayelements on a polycrystalline semiconductor layer in the display areaand peripheral circuitry on a monocrystalline semiconductor layer in theperipheral circuitry area, a process to separate a support substratefrom a porous semiconductor layer of the same supporting substrate, aprocess to attach a backing to an ultra slim electrooptic displayelement substrate after they have been separated and a process to divideassembly into each ultra slim electrooptic display device unit afterattaching the backings.

In this manufacturing process, an ultra slim SOI layer is formed on aporous layer of a support substrate by forming a porous semiconductorlayer and a monocrystalline semiconductor layer on both a seed substrateand on a supporting substrate and by attaching both substrates togethervia an insulating layer and the by separating a seed substrate from theporous semiconductor layer of the seed substrate. After this process,this monocrystalline semiconductor layer of the support substrate needsto be etched, exfoliating the remainder of the porous semiconductorlayer with hydrofluoric acid etchant if necessary, and an insulatinglayer is formed by hydrogen anneal treatment after planarization withetching. The insulating layer of the peripheral circuitry needs to beremoved, while leaving the insulating layer in the display area. Apolycrystalline semiconductor layer is formed in the display area and amonocrystalline semiconductor layer is formed in the peripheralcircuitry by semiconductor epitaxial growth, and the display element areformed on a polycrystalline semiconductor layer in the display area andthe peripheral circuitry is formed on a monocrystalline semiconductorlayer in the peripheral circuitry area. As a result, a polycrystallinesemiconductor TFT display element with low current leakage attributeswith comparatively low high electron and positive hole mobility and apolycrystalline semiconductor TFT display element with high drivabilitythat has high electron and positive hole mobility can be formed on anultra slim SOI layer on a porous layer of the same supporting substrate.By removing the support substrate from the porous semiconductor layerand attaching a backing, then separating each of the ultra slimelectrooptic display device units, you can gain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitthat has high electron and positive hole mobility and low currentleakage attributes.

The manufacturing process for the third ultra slim electrooptic displaydevice unit in this invention includes as follows: processes to formboth a polycrystalline semiconductor layer in the display area and amonocrystalline semiconductor layer in the peripheral area withsemiconductor epitaxial growth by forming an insulating layer on thesupport substrate surface comprised of monocrystalline semiconductorwhile removing an insulating layer in the peripheral circuitry area andleaving an insulating layer in a display area, a process to form bothdisplay elements on a polycrystalline semiconductor layer in the displayarea and peripheral circuitry on a monocrystalline semiconductor layerin the peripheral circuitry area, a process to form an ion implantationlayer to the specified depth in a supporting substrate, a process to doan anneal treatment for exfoliation, a process to separate a supportsubstrate at the deformative area of the ion implantation layer, aprocess to attach a backing to an ultra slim electrooptic displayelement substrate after its separation and a process to divide eachultra slim electrooptic display device unit after attaching thebackings.

In the manufacturing process an insulating layer is formed on thesurface of a support substrate. The insulating layer is then removed inthe peripheral circuitry area while the insulating layer remains in thedisplay area. Then, a polycrystalline semiconductor layer is formed inthe display area and a monocrystalline semiconductor layer is formed inthe peripheral circuitry via semiconductor epitaxial growth. Becausethey both are formed, a polycrystalline semiconductor TFT displayelement which has comparatively low high electron and positive holemobility and low electric current leakage qualities and amonocrystalline semiconductor TFT peripheral circuitry which offers highelectron and positive hole mobility and high drivability can be formedon the same support substrate. By separating the support substrate atthe deformative part of ion implantation layer and attaching a backing,and then dividing the assembly into each ultra slim electrooptic displaydevice units, you can gain a high intensity, high definition andsophisticated ultra slim electrooptic display device unit that has highelectron and positive hole mobility and low current leakage attributes.

The manufacturing process for the fourth ultra slim electrooptic displaydevice unit includes as follows; a process to form an ion implantationlayer on a seed substrate which is comprised of monocrystallinesemiconductor, a process to form an insulating layer on the supportsubstrate which consists of monocrystalline semiconductor, a process toform a monocrystalline semiconductor layer by covalent bonding to theinsulating layer of the support substrate and an ion implantation layerby heat treatment after attaching the ion implantation layer of thesupport substrate and an insulating layer of the support substrate, aprocess to separate a seed substrate at the deformative area of the ionimplantation after an annealing treatment for exfoliation, a process forplanarizing a monocrystalline semiconductor layer surface by etching andwith a minimum a hydrogen anneal treatment, a process to form both apolycrystalline semiconductor layer in the display area and amonocrystalline semiconductor layer in the peripheral circuitry area bysemiconductor epitaxial growth by forming an insulating layer on amonocrystalline semiconductor layer surface where the insulating layeris removed by etching in the peripheral circuitry area while leaving theinsulating layer in the display area, a process to form both displayelements on a polycrystalline semiconductor layer in the display areaand the peripheral circuitry on a monocrystalline semiconductor layer inthe peripheral circuitry area, a process to form an ion implantationlayer to a certain depth in a support substrate, a process to do annealtreatment for exfoliation, a process to separate a support substrate atthe deformative area of an ion implantation layer, a process to attach abacking to an ultra slim electrooptic display element substrate afterit's separation, and a process to divide the assembly into each ultraslim electrooptic display device unit after attaching the backing.

With this manufacturing method, a monocrystalline semiconductor layer isformed by covalent bonding with an ion implantation layer of a seedsubstrate and an insulating layer of a support substrate with heattreatment after attaching the support substrate consisting of aninsulating layer onto a seed substrate which consists of an ionimplantation layer. Then, an ultra slim SOI layer is formed on a supportsubstrate by separating the seed substrate at an ion implantation layerafter anneal treatment for exfoliation and etching the surface of amonocrystalline semiconductor layer with a hydrofluoric acid etchant asrequired, and then, etching and planarizing the surface of amonocrystalline semiconductor layer with a hydrogen anneal treatment. Aninsulating layer is formed on a monocrystalline semiconductor layer ofthis support substrate, and the insulating layer of the peripheralcircuitry area is removed while an insulating layer is left in thedisplay area. A polycrystalline semiconductor layer is formed in thedisplay area by semiconductor epitaxial growth and a monocrystallinesemiconductor layer is formed in a peripheral circuitry area. This formsdisplay elements in a polycrystalline semiconductor TFT layer in thedisplay area and the peripheral circuitry in a monocrystallinesemiconductor layer in the peripheral circuitry area. Because of thisformation, it is possible to form a polycrystalline semiconductor TFTdisplay element which has comparatively low high electron and positivehole mobility and low electric current leakage qualities and amonocrystalline semiconductor TFT peripheral circuitry which has highelectron and positive hole mobility and high drivability on the samesupport substrate. With this, we can obtain a high intensity, highdefinition and sophisticated ultra slim electron-optic display deviceunit which has high electron and positive hole mobility and low electriccurrent leakage qualities by separating the support substrate at thedeformative area of an ion implantation layer and attaching a backing,and then dividing the assembly into each ultra slim electrooptic displaydevice unit.

The manufacturing process for the fifth ultra slim electrooptic displaydevice unit includes the following; a process where an ionimplementation layer is applied to a seed substrate comprised of amonocrystalline semiconductor, a process to form a porous semiconductorlayer on a support substrate which consists of monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layeron a support substrate via a porous semiconductor layer, a process toform an insulating layer on a monocrystalline semiconductor layer, aprocess to form a monocrystalline semiconductor layer by covalentbonding with heat treatment to an ion implementation layer of a seedsubstrate and an insulating layer on a support substrate by attaching anion implementation layer of a seed substrate and an insulating layer ofa support substrate, a process to separate a seed substrate from adeformative area of an ion implementation layer via anneal treatment forexfoliation, a process to planarize and etch the surface of amonocrystalline semiconductor layer with a minimum hydrogen annealtreatment, a process to form both a monocrystalline semiconductor layerfor the peripheral circuitry and a polycrystalline semiconductor layerfor the display area via semiconductor epitaxial growth by forming aninsulating layer on the surface of a monocrystalline semiconductor layerand by removing by etching an insulating layer form the peripheralcircuitry while leaving an insulating layer in the display area, aprocess to form both display elements in a polycrystalline semiconductorlayer in the display area and peripheral circuitry in a monocrystallinesemiconductor layer in the peripheral circuitry area, a process toseparate a support substrate from a porous semiconductor layer, aprocess to attach backings to an ultra slim electrooptic display elementsubstrate after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attachingbackings.

With this manufacturing method, a monocrystalline semiconductor layer isformed by covalent bonding with heat treatment of an ion implantationlayer on the seed substrate and an insulating layer of the supportsubstrate and then by attaching the support substrate which forms aporous semiconductor layer, a monocrystalline semiconductor layer and aninsulating layer as an ion implantation layer forms on the seedsubstrate. The ultra slim SOI layer is formed on the support substrateby separating the seed substrate at an ion implantation layer after theanneal processing for exfoliation and by etching the surface of themonocrystalline semiconductor layer with hydrofluoric acid etchant ifneeded and by etching and planarizing the surface of the monocrystallinesemiconductor layer by a hydrogen anneal processing. After that, aninsulating layer is formed in the monocrystalline semiconductor layer ofthis support substrate and the insulating layer of the peripheralcircuit area is removed while leaving the insulating layer in thedisplay area. A polycrystalline semiconductor layer is formed in thedisplay area and a monocrystalline semiconductor layer is formed in theperipheral circuit area by semiconductor epitaxial growth. Because thedisplay elements are formed in the polycrystalline of the display areaand the peripheral circuit components are formed in the monocrystallinesemiconductor layer of the peripheral circuit area, it is possible toform the polycrystalline semiconductor TFT display elements which haverelatively low high electron and positive hole mobility and low electriccurrent leakage qualities, and a monocrystalline semiconductor TFTperipheral circuit with high electronic hole mobility and highdrivability on the same support substrate. By separating the supportsubstrate from the porous semiconductor layer and attaching the backing,you can obtain a high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities bydividing the assembly into each ultra slim electrooptic display deviceunits.

The manufacturing processes for the sixth ultra slim electroopticdisplay device unit of this invention are as follows; a process to forma porous semiconductor layer in the support substrate which is comprisedof monocrystalline semiconductor, a process to form a monocrystallinesemiconductor layer on the support substrate via a porous semiconductorlayer, a process to form an insulating layer on the surface of themonocrystalline semiconductor layer and furthermore, to form anamorphous semiconductor layer, an amorphous and a polycrystallinemixture semiconductor layer or a polycrystalline semiconductor layer, aprocess to remove the amorphous semiconductor layer, the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer of the peripheral circuit area while leaving theinsulating layer, the amorphous semiconductor layer, the amorphous andpolycrystalline mixture semiconductor layer, or the polycrystallinesemiconductor layer in the display area, a process to form the displayelements in the amorphous semiconductor layer, the amorphous andpolycrystalline mixture semiconductor layer, and the polycrystallinesemiconductor layer of the display area, and the peripherals in themonocrystalline semiconductor layer of the peripheral circuit area, aprocess to separate the support substrate from the porous semiconductorlayer, a process to attach the backing to the ultra slim electroopticdisplay element substrate after its separation, a process to divide theassembly into each ultra slim electrooptic display element unit afterattaching the backing.

With this manufacturing method, a porous semiconductor layer andmonocrystalline semiconductor layer are formed in the support substratewhich consists of monocrystalline semiconductor. An insulating layer andan amorphous semiconductor layer, or the amorphous and polycrystallinemixture semiconductor layer, and the polycrystalline semiconductor layerare formed on the monocrystalline semiconductor layer. The insulatinglayer and amorphous semiconductor layer, or the amorphous andpolycrystalline mixture semiconductor or the polycrystallinesemiconductor is left in the display area. At least the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer isremoved in the peripheral circuit area. The display elements are formedin the amorphous semiconductor layer of the display area or theamorphous and polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer. The peripheral circuit is formed inmonocrystalline semiconductor layer of the peripheral circuit area. Itis possible to form amorphous semiconductor TFT or amorphous andpolycrystalline mixture semiconductor TFT or polycrystallinesemiconductor TFT display elements which have relatively low highelectron and positive hole mobility and low electric current leakagequalities and also a monocrystalline semiconductor TFT peripheralcircuit which will have high electron and positive hole mobility andhigh drivability on the same support substrate. By separating thesupport substrate from the porous semiconductor layer, attaching thebacking, and dividing the assembly into each into separate ultra slimelectrooptic display device units, you can obtain high intensity, highdefinition and sophisticated ultra slim electrooptic display deviceunits that have high electron and positive hole mobility and lowelectric current leakage qualities.

The manufacturing process for the seventh ultra slim electroopticdisplay device unit of this invention includes the following; a processto form a porous semiconductor layer on the seed substrate and thesupport substrate which consists of monocrystalline semiconductor, aprocess to form a monocrystalline semiconductor layer via a poroussemiconductor layer on the seed substrate or support substrate, aprocess to form an insulating layer via a monocrystalline semiconductorlayer on both the seed substrate and the support substrate, a process toattach the seed substrate and the support substrate and an insulatinglayer at the surface, a process to separate the seed substrate from theporous semiconductor layer of the seed substrate, a process to etch andplanarize with a minimum hydrogen anneal processing the surface of themonocrystalline semiconductor layer which was exposed due to theseparation of the seed substrate, a process to form an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor after forming aninsulating layer on the surface of monocrystalline semiconductor layer,a process to remove the insulating layer and the amorphous semiconductorlayer or the amorphous and polycrystalline mixture semiconductor layeror the polycrystalline semiconductor layer in the display area and leavethe amorphous semiconductor layer or the amorphous and polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerin the peripheral circuit area, a process to form the display elementson the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer of the display area, and the peripheral circuitry onthe monocrystalline semiconductor layer of the peripheral circuit area,a process to separate the support substrate from the poroussemiconductor layer of the same support substrate, a process to attachthe backing to the ultra slim electrooptic display element substrateafter its separation, a process to divide the assembly into each ultraslim electrooptic display device unit after attaching the backing.

This manufacturing method forms an ultra slim SOI layer on the porouslayer of the support substrate by forming a porous semiconductor layerand a monocrystalline semiconductor layer on both the seed substrate andsupport substrate, attaching both these substrates via an insulatinglayer, and then by separating the seed substrate from the poroussemiconductor layer of the seed substrate. After that, an amorphoussemiconductor layer or amorphous and polycrystalline mixturesemiconductor layer or polycrystalline semiconductor layer is formedafter etching the monocrystalline semiconductor layer of this supportsubstrate with hydrofluoric acid etchant as required and the remainderof the porous semiconductor layer is treated for exfoliation afteretching and planarizing with a hydrogen anneal processing and aninsulating layer is formed on the surface of the monocrystallinesemiconductor layer.

At least the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer are removed in the peripheral circuit area leavingthe insulating layer and the amorphous semiconductor layer or theamorphous and polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer in the display area. You can make anamorphous semiconductor TFT or an amorphous and polycrystalline mixturesemiconductor TFT or a polycrystalline semiconductor TFT display elementwhich will have relatively low high electron and positive hole mobilityand low electric current leakage quality, and a monocrystallinesemiconductor TFT peripheral circuit which has high electron andpositive hole mobility and high drivability on the ultra slim SOI layerof the porous layer in the same support substrate because it forms thedisplay elements on the amorphous semiconductor layer or the amorphousand polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer in the display area, and the peripheral circuitry onthe monocrystalline semiconductor layer of the peripheral circuit area.You can obtain a high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities byseparating the support substrate from the porous semiconductor layer,attaching the backing and dividing the assembly into each ultra slimelectrooptic display device unit.

The manufacturing method for the eighth ultra slim electrooptic displaydevice unit for this invention includes as follows; a process to form aninsulating layer on the surface of the support substrate which consistsof monocrystalline semiconductor, furthermore it forms an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor layer, a processto remove at a minimum, the amorphous semiconductor layer or theamorphous and polycrystalline mixture semiconductor layer orpolycrystalline semiconductor layer of the peripheral circuit area whileleaving the insulating layer and the amorphous semiconductor layer orthe amorphous and polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer of the display area, a process toform the display elements on the amorphous semiconductor layer or anamorphous and polycrystalline mixture semiconductor layer orpolycrystalline semiconductor of the display area, and form theperipheral circuitry on the monocrystalline semiconductor layer of theperipheral circuit area, a process to form the ion implantation layer toa specified depth on the support substrate, a process to do the annealprocessing for exfoliation, a process to separate the support substratefrom a deformative area of the ion implantation layer, a process toattach the backing to the ultra slim electrooptic display elementsubstrate after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attaching thebacking.

With this manufacturing method, an insulating layer and an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor layer is formedon the surface of the support substrate. Then at a least the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer isremoved in the peripheral circuit area leaving the insulating layer orthe amorphous semiconductor layer or the amorphous and polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerin the display area. It also forms both an amorphous semiconductor layeror an amorphous and polycrystalline mixture semiconductor layer or apolycrystalline semiconductor layer in the display area, and amonocrystalline semiconductor layer in the peripheral circuit area. Itis possible to form an amorphous semiconductor TFT or an amorphous andpolycrystalline mixture semiconductor TFT or a polycrystallinesemiconductor TFT display element which has relatively low high electronand positive hole mobility and low electric current leakage quality, anda monocrystalline semiconductor TFT peripheral circuit which has highelectron and positive hole mobility and high drivability on the samesupport substrate because the display elements are formed in theamorphous semiconductor layer or the amorphous and polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerof the display area and the peripheral circuitry in the monocrystallinesemiconductor layer of the peripheral circuit area. You can obtain ahigh intensity, high definition and sophisticated ultra slimelectrooptic display device unit by attaching the backing afterseparating the support substrate from the deformative area of the ionimplantation layer and dividing the assembly into each ultra slimelectrooptic display device unit.

The manufacturing method for the ninth ultra slim electrooptic displaydevice unit for this invention includes as follows; a process to formthe ion implantation layer on the seed substrate which consists ofmonocrystalline semiconductor, a process to form the insulating layer ofsupport substrate which consists of monocrystalline semiconductor, aprocess to form a monocrystalline semiconductor layer by covalentbonding to the ion implantation layer and an insulating layer on thesupport substrate with heat treatment after attaching to the ionimplantation layer of the seed substrate and an insulating layer of thesupport substrate, a process to separate the seed substrate from adeformative area of ion implantation layer of the same seed substrateafter the anneal processing for exfoliation, a process to etch andplanarize the surface of monocrystalline semiconductor layer with aminimum hydrogen anneal processing, a process to form an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor layer afterforming an insulating layer on the surface of the support substratewhich consists of monocrystalline semiconductor, a process to remove atleast the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer of the peripheral circuit area while leaving theinsulating layer and the amorphous semiconductor layer or the amorphousand polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer in the display area, a process to form displayelements in the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor of the display area, and the peripheral circuitry in themonocrystalline semiconductor layer of the peripheral circuit area, aprocess to form an ion implantation layer of a specified depth on thesupport substrate, a process to do the annealing process forexfoliation, a process to separate the support substrate from adeformative area of ion implantation layer, a process to attach abacking to the ultra slim electrooptic display device unit after itsseparation, and a process to divide each ultra slim electrooptic displaydevice unit after attaching the backing.

With this manufacturing method a monocrystalline semiconductor layer isformed by covalent bonding of the ion implantation layer of the seedsubstrate with heat treatment and the insulating layer of the supportsubstrate by attaching the supporting substrate which consists of theinsulating layer to the seed substrate which consists of the ionimplantation layer. It separates the seed substrate from the ionimplantation layer after the anneal processing for exfoliation.Furthermore, it forms the ultra slim SOI layer on the support substrateby etching and planarizing the surface of the monocrystallinesemiconductor layer with hydrogen anneal processing and by etching thesurface of the monocrystalline semiconductor layer with hydrofluoricacid etchant as required. After that, it forms an insulating layer andan amorphous semiconductor layer or an amorphous and polycrystallinemixture semiconductor layer or a polycrystalline semiconductor layer. Itremoves at least a minimum the amorphous semiconductor layer or theamorphous and polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer of the peripheral circuit arealeaving the insulating layer and the amorphous semiconductor layer orthe amorphous and polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer in display area. This forms theamorphous semiconductor layer or the amorphous and the polycrystallinesemiconductor layer or the polycrystalline semiconductor layer in thedisplay area, and the monocrystalline semiconductor layer in theperipheral circuit area. An amorphous semiconductor TFT or an amorphousand polycrystalline mixture semiconductor TFT or a polycrystallinesemiconductor TFT display element which has relatively low high electronand positive hole mobility and low electric current leakage qualitiesand a monocrystalline semiconductor TFT peripheral circuit which hashigh electron and positive hole mobility and high drivability can beformed on the same support substrate because each display element isformed in the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor or the polycrystallinesemiconductor layer in the display area, and the peripheral circuitry isformed in the monocrystalline semiconductor layer in the peripheralcircuit area. You can obtain a high intensity, high definition andsophisticated ultra slim electrooptic display device unit which has highelectron and positive hole mobility and low electric current leakagequalities by separating the support substrate from the deformative areaof the ion implantation after attaching the backing, and dividing theassembly into each ultra slim electrooptic display device unit.

The manufacturing method for the tenth ultra slim electrooptic displaydevice unit in this invention includes as follows; a process to form anion implantation layer on the seed substrate which consists ofmonocrystalline semiconductor, a process to form a porous semiconductorlayer on the support substrate which consists of monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layervia a polycrystalline semiconductor layer on the support substrate, aprocess to form an insulating layer on the monocrystalline semiconductorlayer, a process to form a monocrystalline semiconductor layer bycovalent bonding the ion implantation layer and the insulating layer ofthe support substrate with heat treatment after attaching the ionimplantation layer of the seed substrate and the insulating layer of thesupport substrate, a process to separate the seed substrate from thedeformative area from ion implantation after the anneal processing forexfoliation, a process to etch and planarize the surface of themonocrystalline semiconductor layer with a minimum hydrogen annealprocessing, a process to form an amorphous semiconductor layer or anamorphous and polycrystalline mixture semiconductor layer or apolycrystalline semiconductor layer after forming an insulating layer onthe surface of the support substrate which consists of monocrystallinesemiconductor, a process to remove at a minimum the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer and the polycrystalline semiconductor layer of theperipheral circuit area leaving the insulating layer and the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer in thedisplay area, a process to form display elements in the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer of thedisplay area, and the peripheral circuitry on the monocrystallinesemiconductor layer of the peripheral circuit area, a process toseparate the support substrate from the porous semiconductor layer, aprocess to attach a backing to the ultra slim electrooptic displaydevice unit after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attaching thebacking.

With this manufacturing method, the seed substrate on which an ionimplantation layer is formed is attached to the support substrate whichforms a porous semiconductor layer, a monocrystalline semiconductorlayer and an insulating layer. It separates the seed substrate in theion implantation layer after the anneal processing for exfoliation, byforming a monocrystalline semiconductor layer and a covalent bonding ionimplantation layer on the seed substrate by heat treatment and aninsulating layer on the support substrate. It forms an ultra slim SOIlayer on the support substrate by etching the surface of monocrystallinesemiconductor layer with hydrofluoric acid etchant as required, and byetching and planarizing the surface of monocrystalline semiconductorlayer with hydrogen anneal processing. Then an insulating layer and anamorphous semiconductor layer or an amorphous and polycrystallinemixture semiconductor layer or a polycrystalline semiconductor layer isformed. At a minimum, the amorphous semiconductor layer or amorphous andthe polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer is removed in the peripheral circuit area leaving aninsulating layer and an amorphous semiconductor layer or an amorphousand polycrystalline mixture semiconductor layer or a polycrystallinesemiconductor layer in the display area. Both an amorphous semiconductorlayer or an amorphous and polycrystalline mixture semiconductor layer ora polycrystalline semiconductor layer is formed in the display area, anda monocrystalline semiconductor layer is formed in the peripheralcircuit area. This forms an amorphous semiconductor TFT or an amorphousand polycrystalline mixture semiconductor TFT or a polycrystallinesemiconductor TFT display element which has relatively low high electronand positive hole mobility and low electric current leakage qualities,and a monocrystalline semiconductor TFT peripheral circuit which hashigh electron and positive hole mobility and high drivability becausethe display elements are formed on an amorphous semiconductor layer oran amorphous and polycrystalline mixture semiconductor layer or apolycrystalline semiconductor layer in the display area and theperipheral circuitry is formed in a monocrystalline semiconductor layerin the peripheral circuit area. With this, you can obtain a highintensity, high definition and sophisticated ultra slim electroopticdisplay device unit which has high electron and positive hole mobilityand low electric current leakage qualities by separating the supportsubstrate from the porous semiconductor layer, attaching the backingsand then dividing the assembly into each ultra slim electrooptic displaydevice unit.

The manufacturing method for the eleventh ultra slim electroopticdisplay device unit for this invention includes the following; a processto form a porous semiconductor layer on the seed substrate and supportsubstrate which consists of monocrystalline semiconductor, a process toform a monocrystalline semiconductor layer via the porous semiconductorlayer on the seed substrate and support substrate, a process to form aninsulating layer via the monocrystalline semiconductor layer on eitherthe seed substrate or the support substrate, a process to attach theseed substrate and support substrate at the surface of the insulatinglayer, a process to separate the seed substrate from the poroussemiconductor layer formed on the seed substrate, a process to etch andplanarize the surface of the monocrystalline semiconductor layer whichis exposed by separating the seed substrate with a minimum hydrogenanneal processing, a process to expose the insulating layer by etchingthe display area of the monocrystalline semiconductor layer, a processto form a polycrystalline semiconductor layer in the display area and amonocrystalline semiconductor layer in the peripheral circuit area withsemiconductor epitaxial growth, a process to form display elements in apolycrystalline semiconductor layer in the display area and theperipheral circuitry in the monocrystalline semiconductor layer in theperipheral circuit area, a process to separate the support substratefrom the porous semiconductor layer of the same support substrate, aprocess to attach a backing to an ultra slim electrooptic displayelement substrate after its separation, and a process to divide eachultra slim electrooptic display device unit after attaching the backing.

With this manufacturing method, an ultra slim SOI layer is formed on aporous layer of the support substrate by forming a porous semiconductorlayer and a monocrystalline semiconductor layer on both seed substrateand the support substrate, attaching both substrates together via aninsulating layer, separating the seed substrate from the poroussemiconductor layer of the seed substrate. After that, a polycrystallinesemiconductor layer is formed in the display area, and a monocrystallinesemiconductor layer is formed in the peripheral circuit by semiconductorepitaxial growth after etching and planarizing the monocrystallinesemiconductor layer of this support substrate with hydrogen annealprocessing and exposing an insulating layer by etching the display areaof a monocrystalline semiconductor layer. It is possible to form apolycrystalline semiconductor TFT display element which has relativelylow high electron and positive hole mobility and low electric currentleakage qualities and a monocrystalline semiconductor TFT peripheralcircuit which has high electron and positive hole mobility and highdrivability on an ultra slim SOI layer of a porous layer on the samesupport substrate because the display element are formed in thepolycrystalline semiconductor layer in the display area while amonocrystalline semiconductor layer is formed in peripheral circuitarea. With this, you can obtain a high intensity, high definition andsophisticated ultra slim electrooptical display device unit which hashigh electron and positive hole mobility and low electric currentleakage qualities, by attaching the backings after separating thesupport substrate from the porous semiconductor layer and dividing theassembly into each ultra slim electrooptic display device unit.

The manufacturing method for the twelfth ultra slim electrooptic displaydevice unit for this invention includes as follows; a process to form anion implantation layer on the seed substrate which consists ofmonocrystalline semiconductor, a process to from an insulating layer onthe support substrate which consists of a monocrystalline semiconductor,a process to form monocrystalline semiconductor layer by covalentbonding with the ion implantation layer and insulating layer with heattreatment after attaching the ion implantation layer of seed substrateand the insulating layer of the support substrate, a process to separatethe seed substrate from a deformative area of the ion implantation layeron the same seed substrate after the anneal processing for exfoliation,a process to etch and planarize the surface of the monocrystallinesemiconductor layer with a minimum the hydrogen annealing process, aprocess to expose the insulating layer by etching the display area ofthe monocrystalline semiconductor layer, a process to form amonocrystalline semiconductor layer in the peripheral circuit area and apolycrystalline semiconductor layer in the display area withsemiconductor epitaxial growth, a process to form display elements inthe polycrystalline semiconductor layer of the display area and theperipheral circuitry in the monocrystalline semiconductor layer ofperipheral circuit area, a process to form an ion implantation layer tothe specified depth on the support substrate, a process to do the annealprocessing for exfoliation, a process to separate the support substratefrom the deformative area of the ionic implantation layer, a process toattach a backing to the ultra slim electrooptic display elementsubstrate after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attaching thebacking.

With this manufacturing method, a monocrystalline semiconductor layer isformed by covalent bonding of the ion implantation layer of the seedsubstrate with heat treatment and the insulating layer of supportsubstrate after attaching the support substrate which forms aninsulating layer onto the seed substrate on which is formed the ionimplantation layer. The ultra slim SOI layer is formed on the supportsubstrate by etching and planarizing the surface of the monocrystallinesemiconductor layer with hydrogen anneal processing by separating theseed substrate from the ion implantation layer after the annealprocessing for exfoliation. After that, a polycrystalline semiconductorlayer is formed in the display area and a monocrystalline semiconductorlayer is formed in the peripheral circuit area by semiconductorepitaxial growth after exposing the insulating layer by etching thedisplay area of the monocrystalline semiconductor layer. Apolycrystalline semiconductor TFT display element is formed, which hasrelatively low high electron and positive hole mobility and low electriccurrent leakage qualities, and a monocrystalline semiconductor TFTperipheral circuit which has high electron and positive hole mobilityand high drivability on the same substrate because it forms a displayarea in polycrystalline semiconductor layer of the display area andperipheral circuitry in a monocrystalline semiconductor layer of theperipheral circuit area. With this, you can obtain a high intensity,high definition and sophisticated ultra slim electrooptic display deviceunit that has high electron and positive hole mobility and low electriccurrent leakage qualities by attaching the backing after separating thesupport substrate from a deformative area of the ion implantation layerand dividing the assembly into each ultra slim electrooptic displaydevice unit.

The manufacturing method for the thirteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists ofmonocrystalline semiconductor, a process to form a porous semiconductorlayer on the support substrate which consists of monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layeron the support substrate via a porous semiconductor, a process to forman insulating layer on the monocrystalline semiconductor layer, aprocess to form a monocrystalline semiconductor layer by covalentbonging with the ion implantation layer of seed substrate with heattreatment and insulating layer of support substrate after attaching theion implantation layer of the seed substrate and the insulating layer ofthe support substrate, a process to separate the seed substrate from thedeformative area of the ion implantation layer after the annealprocessing for exfoliation, a process to etch and planarize the surfaceof the monocrystalline semiconductor layer with a minimum hydrogenanneal processing, a process to expose the insulating layer by etchingthe display area of monocrystalline semiconductor layer, a process toform polycrystalline semiconductor layer in the display area, andmonocrystalline semiconductor layer in peripheral circuit area withsemiconductor epitaxial growth, a process to form display elements inthe monocrystalline semiconductor layer of the display area andperipheral circuitry in the monocrystalline semiconductor layer of theperipheral circuit, a process to separate the support substrate from theporous semiconductor layer, a process to attach a backing to the ultraslim electrooptic display element substrate after its separation, aprocess to divide the assembly into each ultra slim electrooptic displaydevice unit after attaching the backing.

With this manufacturing method, a monocrystalline semiconductor layer isformed by covalent bonding ion implantation of the seed substrate withheat treatment and the insulating layer of the support substrate afterattaching the support substrate which forms a porous semiconductorlayer, monocrystalline semiconductor and insulating layer to the seedsubstrate on which is formed an ion implantation layer. The supportsubstrate is separated at the ion implantation layer after annealprocessing for exfoliation, an ultra slim SOI layer is formed on thesupport substrate by etching and planarizing the surface of themonocrystalline semiconductor layer with hydrogen anneal processing forexfoliation. After that, the polycrystalline semiconductor layer in thedisplay area and monocrystalline semiconductor layer in the peripheralcircuit are formed with semiconductor epitaxial growth by etching thedisplay area of the monocrystalline semiconductor layer and by exposingthe insulating layer. The polycrystalline semiconductor TFT displayelement which exhibits relatively low high electron and positive holemobility and low electric current leakage qualities and amonocrystalline semiconductor TFT peripheral circuit which exhibits highelectron and positive hole mobility and high drivability can be formedon the same support substrate because it forms the display elements areformed in the polycrystalline semiconductor layer of the display areaand the peripheral circuitry is formed in the monocrystallinesemiconductor layer in the peripheral circuit area. You can obtain ahigh intensity, high definition and sophisticated ultra slimelectrooptic display device unit that has high electron and positivehole mobility and low electric current leakage qualities by dividing theassembly into each ultra slim electrooptic display device unit afterseparating the support substrate from the porous semiconductor layerafter attaching the backing.

The manufacturing method for the fourteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform a porous semiconductor layer on the support substrate whichconsists of monocrystalline semiconductor, a process to form amonocrystalline semiconductor on the seed substrate and the supportsubstrate via a porous semiconductor layer, a process to form aninsulating layer via monocrystalline semiconductor layer on either theseed substrate or the support substrate, a process to attach the seedsubstrate and support substrate at the surface where the insulatinglayer was formed, a process to separate the seed substrate from theporous semiconductor layer of the seed substrate, a process to etch andplanarize the surface of monocrystalline semiconductor layer which isexposed by the separation of the seed substrate with a minimum hydrogenanneal processing, a process to expose the insulating layer by etchingthe display area of the monocrystalline semiconductor layer, a processto form an insulating film and amorphous semiconductor layer or anamorphous and polycrystalline mixture semiconductor layer or apolycrystalline semiconductor layer, a process to form display elementsin an amorphous semiconductor layer or an amorphous and polycrystallinemixture semiconductor layer or a polycrystalline mixture semiconductorlayer or polycrystalline semiconductor layer in the display area andperipheral circuitry in the monocrystalline semiconductor layer in theperipheral circuit area in which at least the amorphous semiconductorlayer or the amorphous and polycrystalline mixture semiconductor layeror the polycrystalline semiconductor layer is etched, a process toseparate the support substrate from the porous semiconductor layer ofthe same support substrate, a process to attach a backing to the ultraslim electrooptic display element substrate after its separation, aprocess to divide the assembly into each ultra slim electrooptic displaydevice unit after attaching the backing.

With this manufacturing method, an ultra slim SOI layer is formed on aporous layer of the support substrate by separating the seed substratein the porous semiconductor layer of the seed substrate via theinsulating layer after forming the porous semiconductor layer andmonocrystalline semiconductor layer on both of the seed substrate andsupport substrate and by attaching an insulating layer via thesesubstrates. After that, the insulating film and the amorphoussemiconductor layer or the amorphous and polycrystalline semiconductorlayer or the polycrystalline semiconductor layer are formed on theentire area after etching and planarizing the monocrystallinesemiconductor layer of this support substrate with hydrogen annealprocessing and by etching the display area of the monocrystallinesemiconductor layer after exposing the insulating layer. It is possibleto form an amorphous semiconductor TFT or an amorphous andpolycrystalline mixture semiconductor TFT or a polycrystallinesemiconductor TFT display element which has relatively low high electronand positive hole mobility and low electric current leakage qualitiesand a monocrystalline semiconductor TFT peripheral circuit which hashigh electron and positive hole mobility and high drivability on theultra slim SOI layer of the porous layer in the same support substratebecause the display element is formed in the amorphous semiconductorlayer or the amorphous and the polycrystalline mixture semiconductorlayer or the polycrystalline semiconductor layer of the display area andthe peripheral circuitry is formed in the monocrystalline semiconductorlayer of the peripheral circuit area which is etched by a minimum theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layer.With this, you can obtain a high intensity, high definition andsophisticated ultra slim electrooptic display device unit which has highelectron and positive hole mobility and low electric current leakagequalities by attaching the backings after separating the supportsubstrate from the porous semiconductor layer and dividing the assemblyinto each ultra slim electrooptic display device unit.

The manufacturing process for the fifteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer in the seed substrate which is comprisedof monocrystalline semiconductor, a process to form an insulating layeron the support substrate which is comprised of a monocrystallinesemiconductor layer, a process to form a monocrystalline semiconductorlayer by covalent bonding ion implantation layer and an insulating layerwith heat treatment after attaching an ion implantation layer to theseed substrate and an insulating layer of the support substrate, aprocess to separate the seed substrate from deformative part of the ionimplantation layer of the same seed substrate after the annealprocessing for exfoliation, a process to etch and planarize the surfaceof the monocrystalline semiconductor layer with a minimum hydrogenanneal processing, a process to expose the insulating layer afteretching in the display area of the monocrystalline semiconductor layer,a process to form an insulating film and an amorphous semiconductorlayer or an amorphous and polycrystalline mixture semiconductor layer ora polycrystalline semiconductor layer, a process to form displayelements in the amorphous semiconductor layer or the amorphous andpolycrystalline semiconductor layer or the polycrystalline semiconductorlayer of the display area, and peripheral circuitry in themonocrystalline semiconductor layer of peripheral circuit area on whichwas etched at least the amorphous semiconductor layer or the amorphousand polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer, a process to form an ion implantation layer of aspecified depth on the support substrate, a process to do annealprocessing for exfoliation, a process to separate the support substratefrom the deformative area of the ion implantation layer, a process toattach a backing to the ultra slim electrooptic display elementsubstrate after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attaching thebacking.

With this manufacturing method, the support substrate on which aninsulating layer is formed and the seed substrate on which an ionimplantation layer is formed, are attached, and a monocrystallinesemiconductor layer is formed by covalent bonding of the ionimplantation layer of the seed substrate and insulating layer of thesupport substrate with heat treatment, then the seed substrate isseparated at the ion implantation layer after the anneal processing forexfoliation, and an ultra slim SOI layer is formed on the supportsubstrate by etching and planarizing the surface of the monocrystallinesemiconductor layer with the hydrogen anneal processing. After that, theinsulating layer is exposed by etching the display area of themonocrystalline semiconductor layer. It is possible to form an amorphoussemiconductor TFT or an amorphous and a polycrystalline mixturesemiconductor TFT or a polycrystalline semiconductor TFT display elementwhich has relatively low high electron and positive hole mobility andlow electric current leakage quality, and a monocrystallinesemiconductor TFT peripheral circuit which has high electron andpositive hole mobility and high drivability on the same supportsubstrate because an amorphous semiconductor layer or an amorphous andpolycrystalline mixture semiconductor or a polycrystalline semiconductorlayer is formed in the display area, and peripheral circuitry in amonocrystalline semiconductor layer of the peripheral circuit area whichhas had at least the amorphous semiconductor layer or the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer etched and by having a process to form an insulatingfilm and an amorphous semiconductor layer or an amorphous andpolycrystalline mixture semiconductor layer or a polycrystallinesemiconductor layer in the entire area with plasma CVD, heat CVD,sputtering and evaporation. You can obtain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitthat has high electron and positive hole mobility and low electriccurrent leakage qualities by dividing the assembly into each ultra slimelectrooptic display device unit after separating the support substratefrom the porous semiconductor layer after attaching the backing.

The manufacturing process for the sixteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists ofthe monocrystalline semiconductor, a process to from a poroussemiconductor layer on the support substrate which consists ofmonocrystalline semiconductor, a process to form a monocrystallinesemiconductor layer on the support substrate via a porous semiconductorlayer, a process to form an insulating layer on the monocrystallinesemiconductor layer, a process to form a monocrystalline semiconductorlayer by covalent bonding of the ion implantation layer of the seedsubstrate and the insulating layer of the support substrate with heattreatment after attaching ion implantation layer of the seed substrateand insulating layer of the support substrate, a process to separate theseed substrate from the deformative area of the ion implantation layerafter the anneal processing for exfoliation, a process to etch andplanarize the surface of the monocrystalline semiconductor layer with aminimum hydrogen annealing process, a process to expose the insulatinglayer by etching the display area of the monocrystalline semiconductorlayer, a process to form an insulating film and an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor layer in theentire area, a process to form display elements on an amorphoussemiconductor layer or an amorphous and polycrystalline mixturesemiconductor layer or a polycrystalline semiconductor layer of thedisplay area, and peripheral circuitry in a monocrystallinesemiconductor layer of the peripheral circuit area of which at least anamorphous semiconductor layer or an amorphous and polycrystallinemixture semiconductor layer or a polycrystalline semiconductor layer isetched, a process to separate the support substrate from the poroussemiconductor layer, a process to attach a backing to the ultra slimelectrooptic display element substrate after its separation, a processto divide the assembly into each ultra slim electrooptic display deviceunit after attaching the backing.

With this manufacturing method, a monocrystalline semiconductor layer isformed by covalent bonding of the ion implantation layer of the seedsubstrate and the insulating layer of support substrate with heattreatment after attaching the support substrate which forms a poroussemiconductor layer, a monocrystalline semiconductor layer and aninsulating layer on the seed substrate which is formed by ionimplantation. The ultra slim SOI layers is formed on the supportsubstrate by separating the seed substrate at the ion implantationlayer, by anneal processing for exfoliation and by etching andplanarizing the surface of monocrystalline semiconductor layer withhydrogen anneal processing for exfoliation. Then the insulating layer isexposed, and the display area of monocrystalline semiconductor layer isetched and the insulating film and amorphous semiconductor layer oramorphous and polycrystalline mixture semiconductor or polycrystallinesemiconductor are formed in the entire area. It is possible to form anamorphous semiconductor TFT or an amorphous and polycrystalline mixturesemiconductor TFT or a polycrystalline semiconductor TFT display elementwhich has relatively low high electron and positive hole mobility andlow electric current leakage qualities and a monocrystallinesemiconductor TFT peripheral circuit which has high electron andpositive hole mobility and high drivability are formed on the samesupport substrate because the display element is formed in the amorphoussemiconductor layer or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer of thedisplay area and the peripheral circuitry is formed in themonocrystalline semiconductor layer of the peripheral circuit area whichis etched by a minimum the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer. With this, you can obtain a highintensity, high definition and sophisticated ultra slim electroopticdisplay device unit which has high electron and positive hole mobilityand low electric current leakage qualities by attaching the backingsafter separating the support substrate from the porous semiconductorlayer and dividing the assembly into each ultra slim electroopticdisplay device unit.

The manufacturing process for the seventeenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform a porous semiconductor layer on the seed substrate and the supportsubstrate which consists of monocrystalline semiconductor, a process toform a monocrystalline semiconductor layer on the seed substrate and thesupport substrate via a porous semiconductor layer, a process to form aninsulating layer either on the seed substrate or the support substratevia a monocrystalline semiconductor layer, a process to attach the seedsubstrate and the support substrate with an insulating layer formed atthe surface, a process to separate the seed substrate from the poroussemiconductor layer of the same seed substrate, a process to etch andplanarize the surface of the monocrystalline semiconductor layer whichwas exposed by separating the seed substrate with a minimum hydrogenannealing process, a process to expose the insulating layer by etchingthe display area of the monocrystalline semiconductor layer, a processto form the light shielding metallic layer on the polycrystallinesemiconductor display element formation area inside the display area, aprocess to cover the insulating layer, a process to form apolycrystalline semiconductor layer in the display area andmonocrystalline semiconductor layer in the peripheral circuit area withsemiconductor epitaxial growth, a process to form display elements inthe polycrystalline semiconductor layer of the display area and theperipheral circuitry in the monocrystalline semiconductor layer of theperipheral circuit area, a process to separate the support substratefrom the porous semiconductor layer of the same support substrate, aprocess to attach a backing to the ultra slim electrooptic displayelement substrate after its separation, a process to divide the assemblyinto each ultra slim electrooptic display device unit after attachingthe backing.

With this manufacturing method, an ultra slim SOI layer is formed on theporous layer of the support substrate by forming a porous semiconductorlayer and a monocrystalline semiconductor layer on both the seedsubstrate and the support substrate and by attaching both thesesubstrates via an insulating layer and by separating the seed substrateat the porous semiconductor layer of the seed substrate. Then theinsulating layer is exposed by etching the display area of themonocrystalline semiconductor layer after etching and planarizing themonocrystalline semiconductor layer of the support substrate withhydrogen anneal processing. The light-shielding metallic film is formedby patterning and forming the light-shielding metallic film of atransitional metallic silicide such as WSi₂(Tungsten silicide),TiSi₂(Titanium silicide) MoSi₂(Molybdenum silicide), etc. with CVD andsputtering, etc. in the monocrystalline semiconductor display elementforming area inside the display area. The insulating layer is formed ontop of that. The polycrystalline semiconductor layer in the display areaand monocrystalline semiconductor layer in the peripheral circuit areformed with semiconductor epitaxial growth.

It possible to form a polycrystalline semiconductor TFT display elementon the light-shielding metallic film which has relatively low highelectron and positive hole mobility and low electric current leakagequalities and a monocrystalline semiconductor layer which has highelectron and positive hole mobility and increased drivability, and amonocrystalline semiconductor TFT peripheral circuit which is in thehigher monocrystalline half in the peripheral circuit area of the ultraslim SOI layer of the porous layer of the same support substrate becausethe peripheral circuit is formed in the monocrystalline semiconductorlayer of the peripheral circuit area and display element is formed inthe polycrystalline semiconductor layer of the display area.

With this, you can obtain a high intensity, high definition andsophisticated ultra slim electrooptic display device unit which has highelectron and positive hole mobility and low electric current leakagequalities by attaching the backings after separating the supportsubstrate from the porous semiconductor layer and dividing the assemblyinto each ultra slim electrooptic display device unit.

The manufacturing process for the eighteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists of amonocrystalline semiconductor layer, a process to form an insulatinglayer on the support substrate which consists of monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layerby attaching the ion implantation layer of the seed substrate and theinsulating layer of the support substrate and by covalent bonding theion implantation layer and the insulating layer with heat treatment, aprocess to separate the seed substrate from the deformative area of theion implantation layer in the same seed substrate by the annealingprocess for exfoliation, a process to etch and planarize the surface ofthe monocrystalline semiconductor layer with a minimum hydrogen annealprocessing, a process to expose the insulating layer by etching thedisplay area of the monocrystalline semiconductor layer, a process toform an light shielding metallic layer in the polycrystallinesemiconductor display element formation area in the display area, aprocess to cover this with an insulating layer, a process to form apolycrystalline semiconductor layer in the display area andmonocrystalline semiconductor layer in the peripheral circuit area withsemiconductor epitaxial growth, a process to form the peripheral circuitin the monocrystalline semiconductor layer of the peripheral circuit anddisplay elements in the polycrystalline semiconductor layer of thedisplay area, a process to form an ion implantation layer at thespecified depth of the support substrate, a process to do annealprocessing for exfoliation, a process to separate the support substratefrom the deformative area of the ion implantation layer, a process toattach the backing to the ultra slim electrooptic display elementsubstrate after its separation, a process to divide the assembly intoeach ultra slim electrooptic display device unit after attaching thebacking.

The support substrate on which the insulating layer is formed isattached to the seed substrate on which the ion implantation layer isformed, the monocrystalline semiconductor layer is formed by covalentbonding the ion implantation layer of the seed substrate and insulatinglayer of the support substrate with heat treatment, the seed substrateis separated at the ion implantation layer after the anneal processingfor exfoliation. Furthermore, the ultra slim SOI layer is formed on thesupport substrate by etching and planarizing the surface of themonocrystalline semiconductor layer with hydrogen anneal processing.Then, the display area of the monocrystalline semiconductor layer isetched, exposing the insulating layer, the light shielding metalliclayer is formed by patterning and forming with CVD, sputtering, etc. oflight-shielding metallic film of a transitional metallic silicide suchas WSi₂ (Tungsten silicide), TiSi₂ (Titanium silicide) MoSi₂ (Molybdenumsilicide), etc. in the polycrystalline semiconductor display elementformation area inside the display area. The insulating layer is formedon top of the polycrystalline semiconductor layer in the display areaand a monocrystalline semiconductor layer is formed in the peripheralcircuit with semiconductor epitaxial growth. Because the display elementin the polycrystalline semiconductor layer of the display area and theperipheral circuit in the monocrystalline semiconductor layer of theperipheral circuit are formed, it is possible to form a polycrystallinesemiconductor TFT display element which has relatively low high electronand positive hole mobility and low electric current leakage qualitieswhich forms on the light shielding metallic layer and a monocrystallinesemiconductor TFT peripheral circuit which has high electron andpositive hole mobility and high drivability on the ultra slim SOI layerof the top of a porous layer of the same support substrate. With this,you can obtain a high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities byattaching the backings after separating the support substrate from theporous semiconductor layer and dividing the assembly into each ultraslim electrooptic display device unit.

The manufacturing process for the nineteenth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists ofmonocrystalline semiconductor, a process to form a porous semiconductorlayer on the support substrate which consists of monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layeron the support substrate via the porous semiconductor layer, a processto form an insulating layer on the monocrystalline semiconductor layer,a process to form a monocrystalline semiconductor layer by attaching theion implantation layer of the seed substrate and the insulating layer ofthe support substrate and by covalent bonding the ion implantation layerand the insulating layer with heat treatment, a process to separate theseed substrate from the deformative area of the ion implantation layerafter the annealing process for exfoliation, a process to etch andplanarize the surface of the monocrystalline semiconductor layer with aminimum hydrogen anneal processing, a process to expose the insulatinglayer after etching the display area of the monocrystallinesemiconductor layer, a process to form the light shielding metalliclayer in the polycrystalline semiconductor display element formationarea inside the display area, a process to cover the insulating layer, aprocess to cover on top of the insulating area with the insulatinglayer, a process to form a polycrystalline semiconductor layer in thedisplay area and monocrystalline semiconductor in the peripheral circuitarea with semiconductor epitaxial growth, a process to form the displayelement in the polycrystalline semiconductor layer of the display areaand the peripheral circuitry in the monocrystalline semiconductor layerof the peripheral circuit area, a process to separate the supportsubstrate from the porous semiconductor layer, a process to attach abacking to the ultra slim electrooptic display element substrate afterits separation, a process to divide the assembly into each ultra slimelectrooptic display device unit after attaching the backing.

With this manufacturing method, the support substrate which forms theporous semiconductor layer, the monocrystalline semiconductor layer andthe insulating layer which is formed by ion implantation is attached tothe seed substrate. The monocrystalline semiconductor layer is formed bycovalent bonding the ion implantation layer of the seed substrate andthe insulating layer of the support substrate with heat treatment, theseed substrate is separated at the ion implantation layer after theannealing process for exfoliation. Furthermore, an ultra slim SOI layeris formed on the support substrate by etching and planarizing thesurface of the monocrystalline semiconductor layer with the hydrogenannealing process. Then the insulating layer is exposed by etching thedisplay area of the monocrystalline semiconductor layer. The lightshielding metallic layer is formed by patterning the light-shieldingmetallic film of a transitional metallic silicide such as WSi₂ (Tungstensilicide), TiSi₂ (Titanium silicide) MoSi₂ (Molybdenum silicide), etc.with CVD and sputtering, etc. in the polycrystalline semiconductordisplay element formation area of the display area. The insulating layeris formed on top of the light shielding metallic layer. Thepolycrystalline semiconductor layer is formed in the display area andthe monocrystalline semiconductor layer is formed in the peripheral areaby semiconductor epitaxial growth. The polycrystalline mixturesemiconductor TFT or a polycrystalline semiconductor TFT display elementwhich has relatively low high electron and positive hole mobility andlow electric current leakage qualities and a monocrystallinesemiconductor TFT peripheral circuit which has high electron andpositive hole mobility and high drivability on the ultra slim SOI layerof the porous layer in the same support substrate because the displayelement is formed in the display area and the peripheral circuitry isformed in the monocrystalline semiconductor layer of the peripheralcircuit area which is etched by a minimum the amorphous semiconductorlayer or the amorphous and the polycrystalline mixture semiconductorlayer or the polycrystalline semiconductor layer. With this, you canobtain a high intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities by attachingthe backings after separating the support substrate from the poroussemiconductor layer and dividing the assembly into each ultra slimelectrooptic display device unit.

The manufacturing process for the twentieth ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform the porous semiconductor layer on the support substrate and seedsubstrate which consists of a monocrystalline semiconductor, a processto form the monocrystalline semiconductor layer on the seed substrateand the support substrate via the porous semiconductor layer, a processto form the insulating layer via the monocrystalline semiconductoreither on the seed substrate or the support substrate, a process toattach the seed substrate and the support substrate together at theinsulating layer formation surface, a process to separate the seedsubstrate from the porous semiconductor layer of the same seedsubstrate, a process to etch and planarize the surface of themonocrystalline semiconductor layer, which is exposed by the separationof the seed substrate with a minimum of the hydrogen annealing process,a process to expose the insulating layer after etching the display areaof the monocrystalline semiconductor layer, a process to form the lightshielding metallic layer in the amorphous semiconductor or amorphous andpolycrystalline mixture semiconductor or polycrystalline semiconductordisplay element formation area inside the display area, a process toform an insulating layer and the amorphous semiconductor layer over theentire area or an amorphous and polycrystalline semiconductor layer or apolycrystalline semiconductor layer, a process to form the displayelements in the amorphous semiconductor layer, the amorphous andpolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer of the display area, and the peripheral circuit areaof which at least the amorphous semiconductor layer or the amorphous andthe polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer is etched, a process to separate the supportsubstrate from the porous semiconductor layer of the same supportsubstrate, a process to attach a backing to the ultra slim electroopticdisplay element substrate after its separation, a process to divide theassembly into each ultra slim electrooptic display device unit afterattaching the backing.

With this manufacturing process, the porous semiconductor layer andmonocrystalline semiconductor layer are formed on both of the seedsubstrate and the support substrate. These substrates are attached viathe insulating layer. The ultra slim SOI layer is formed on the porouslayer of the support substrate by separating the seed substrate at theporous semiconductor layer of the seed substrate. Then the insulatinglayer is exposed by etching the display area of the monocrystallinesemiconductor layer after etching and planarizing the monocrystallinesemiconductor layer of the support substrate with a hydrogen annealingtreatment. An light-shielding metallic film is created by forming andpatterning the light-shielding metallic film of a transitional metallicsilicide such as WSi₂ (Tungsten silicide), TiSi₂ (Titanium silicide)MoSi₂ (Molybdenum silicide), etc. by CVD and sputtering, etc. in anamorphous semiconductor layer or an amorphous and polycrystallinemixture semiconductor or the polycrystalline semiconductor displayelement formation area of the display area. It is possible to form anamorphous semiconductor TFT or an amorphous and polycrystalline mixturesemiconductor TFT or a polycrystalline semiconductor TFT display elementwhich has relatively low high electron and positive hole mobility andlow electric current leakage qualities on the light shielding metalliclayer, and a monocrystalline semiconductor TFT peripheral circuit whichhas high electron and positive hole mobility and high drivability in theperipheral circuit area on the ultra slim SOI layer of the porous layerof the same support substrate because the display element in theamorphous semiconductor layer or the amorphous and polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerof the display area and the peripheral circuit in the monocrystallinesemiconductor layer of the peripheral circuit area where at least theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerare etched and are formed on the ultra slim SOI layer on the porouslayer of the same support substrate. With this, you can obtain a highintensity, high definition and sophisticated ultra slim electroopticdisplay device unit which has high electron and positive hole mobilityand low electric current leakage qualities by attaching the backingsafter separating the support substrate from the porous semiconductorlayer and dividing the assembly into each ultra slim electroopticdisplay device unit.

The manufacturing process for the twenty first ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists ofthe monocrystalline semiconductor, a process to form an insulating layeron the support substrate which consists of a monocrystallinesemiconductor, a process to form a monocrystalline semiconductor layerby attaching the ion implantation layer of the seed substrate and theinsulating layer of the support substrate and by covalent bonding theion implantation layer and the insulating layer with heat treatment, aprocess to separate the seed substrate from the deformative area of theion implantation layer after the annealing process for exfoliation, aprocess to etch and planarize the surface of the monocrystallinesemiconductor layer with a minimum of hydrogen anneal processing, aprocess to expose the insulating layer after etching the display area ofthe monocrystalline semiconductor layer, a process to form the lightshielding metallic layer on the amorphous semiconductor in the displayarea or an amorphous and polycrystalline mixture semiconductor or thepolycrystalline semiconductor display element formation area, a processto form the insulating layer in the entire area and the amorphoussemiconductor layer or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer, aprocess to form the display element on the amorphous semiconductor layeror the amorphous and the polycrystalline mixture semiconductor layer orthe polycrystalline semiconductor layer of the display area and theperipheral circuit on the monocrystalline semiconductor layer in theperipheral circuit area of which was etched at least the amorphoussemiconductor layer or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer, aprocess to form the ion implantation layer at the specified depth of thesupport substrate, a process to do the anneal processing forexfoliation, a process to separate the support substrate from thedeformative area of the ion implantation layer, a process to attach abacking to the ultra slim electrooptic display element substrate afterits separation, a process to divide the assembly into each ultra slimelectrooptic display device unit after attaching the backing.

With this manufacturing method, the support substrate which forms theinsulating layer is attached onto the seed substrate on which the ionimplantation is formed. A monocrystalline semiconductor layer is formedby covalent bonding of the ion implantation of the seed substrate andthe insulating layer of the support substrate with heat treatment, theseed substrate is separated at the ion implantation layer after theanneal processing for exfoliation, then an ultra slim SOI layer isformed on the support substrate by etching and planarizing the surfaceof the monocrystalline semiconductor layer with hydrogen annealprocessing. After that, the insulating layer is exposed by etching thedisplay area of the monocrystalline semiconductor layer. Thelight-shielding metallic film is formed by forming and patterning atransitional metallic silicide of light-shielding metallic film such asWSi₂ (Tungsten silicide), TiSi₂ (Titanium silicide) MoSi₂ (Molybdenumsilicide) with CVD and sputtering, etc. on the amorphous semiconductorof the display area or the amorphous and polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor display elementformation area. The insulating layer and the amorphous semiconductorlayer or the amorphous and the polycrystalline mixture semiconductorlayer or the polycrystalline semiconductor layer is formed. Theamorphous semiconductor TFT or the amorphous and the polycrystallinemixture semiconductor TFT or the polycrystalline semiconductor TFTdisplay element which are formed on the light shielding metallic layer,have relatively low high electron and positive hole mobility and lowelectric current leakage qualities and the polycrystalline semiconductorTFT peripheral circuit which has high electric positive holy mobilityand high drivability are formed on the ultra slim SOI layer on theporous layer of the same support substrate because the display elementis formed on the amorphous semiconductor layer in the display area orthe amorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer, and the peripheral circuit isformed on the monocrystalline semiconductor layer of the peripheralcircuit area which has etched at least the amorphous semiconductor layeror the amorphous and the polycrystalline mixture semiconductor or thepolycrystalline semiconductor layer are formed on the porous layer ofthe same support substrate. With this, you can obtain a high intensity,high definition and sophisticated ultra slim electrooptic display deviceunit which has high electron and positive hole mobility and low electriccurrent leakage qualities by attaching the backings after separating thesupport substrate from the porous semiconductor layer and dividing theassembly into each ultra slim electrooptic display device unit.

The manufacturing process for the twenty second ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform an ion implantation layer on the seed substrate which consists of amonocrystalline semiconductor, a process to form a porous semiconductorlayer on the support substrate which consists of the monocrystallinesemiconductor layer, a process to form the monocrystalline semiconductorlayer through the porous semiconductor layer on the support substrate, aprocess to form the insulating layer on the monocrystallinesemiconductor layer, a process to form a monocrystalline semiconductorlayer by attaching the ion implantation layer of the seed substrate andthe insulating layer of the support substrate and by covalent bondingthe ion implantation layer and the insulating layer with heat treatment,a process to separate the seed substrate from the deformative area ofthe ion implantation layer after anneal processing for exfoliation, aprocess to etch and planarize the surface of the monocrystallinesemiconductor layer with a minimum hydrogen anneal processing, a processto expose the insulating layer after etching the display area of themonocrystalline semiconductor layer, a process to form the lightshielding metallic layer of the amorphous semiconductor inside thedisplay area or the amorphous and polycrystalline mixture semiconductorinside the display area or the polycrystalline semiconductor displayelement formation area, a process to form the insulating layer and theamorphous semiconductor in the entire area and the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer, a process to form the display element on theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerof the display area and the peripheral circuit on the monocrystallinesemiconductor layer in the peripheral circuit area of which was etchedat least the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer, a process to attach a backing to the ultra slimelectrooptic display element substrate after its separation, a processto divide the assembly into each ultra slim electrooptic display deviceunit after attaching the backing.

With this manufacturing method, the support substrate on which theporous semiconductor layer, the monocrystalline semiconductor layer andthe insulating layer are formed is attached to the seed substrate onwhich the ion implantation layer forms. The monocrystallinesemiconductor layer is formed by covalent bonding the ion implantationlayer of the seed substrate and the insulating layer of the supportsubstrate with heat treatment, the seed substrate is separated at theion implantation layer after anneal processing for exfoliation, theultra slim SOI layer on the support substrate is formed by etching andplanarizing the surface of the monocrystalline semiconductor layer withhydrogen anneal processing. The insulating layer is exposed by etchingthe monocrystalline semiconductor layer of the display area. Then thelight-shielding metallic film is formed by forming and patterning thelight-shielding metallic film of a transitional metallic silicide suchas WSi₂ (Tungsten silicide), TiSi₂ (Titanium silicide), MoSi₂(Molybdenum silicide), etc. with CVD and sputtering, etc. in theamorphous semiconductor inside the display area or the amorphous andpolycrystalline mixture semiconductor or the polycrystallinesemiconductor display element formation area. The insulating layer andthe amorphous semiconductor layer extensively or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer is formed. The amorphous semiconductor TFT or theamorphous and the polycrystalline mixture semiconductor TFT or thepolycrystalline semiconductor TFT display element which are formed onthe light shielding metallic layer, have relatively low high electronand positive hole mobility and low electric current leakage qualitiesand the polycrystalline semiconductor TFT peripheral circuit which hashigh electric positive holy mobility and high drivability are formed onthe ultra slim SOI layer on the porous layer of the same supportsubstrate because the display element is formed on the amorphoussemiconductor layer in the display area or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer, and the peripheral circuit is formed on themonocrystalline semiconductor layer of the peripheral circuit area whichhas etched at least the amorphous semiconductor layer or the amorphousand the polycrystalline mixture semiconductor or the polycrystallinesemiconductor layer are formed on the porous layer of the same supportsubstrate. With this, you can obtain a high intensity, high definitionand sophisticated ultra slim electrooptic display device unit which hashigh electron and positive hole mobility and low electric currentleakage qualities by attaching the backings after separating the supportsubstrate from the porous semiconductor layer and dividing the assemblyinto each ultra slim electrooptic display device unit.

The manufacturing process for the twenty third ultra slim electroopticdisplay device unit in this invention includes as follows; a process toform the a polycrystalline semiconductor layer where the crystal grainsize is controlled by solid phase deposition after stratifying theamorphous semiconductor layer with selectively ion implantation or withion doping of at least one kind of four families of elements (Si, Ge,tin and lead, etc.) in the polycrystalline semiconductor layer of thedisplay area, in the aforementioned claim, sections 1˜5, 11˜13 and17˜19, a process to form the display elements on the polycrystallinesemiconductor layer of the display area where the crystal grain size iscontrolled and the peripheral circuit area on the monocrystallinesemiconductor layer of the peripheral circuit area.

With this manufacturing method, the monocrystalline semiconductor layerin the peripheral circuit area and the polycrystalline semiconductorlayer in the display area are formed by semiconductor epitaxial growthin the aforementioned claim, sections 1˜5, 11˜13, and 11˜17. Thepolycrystalline semiconductor TFT display element which has relativelycontrolled high electron and positive hole mobility and low electriccurrent leakage qualities and the monocrystalline semiconductor TFTperipheral circuit which has high electron and positive hole mobilityand high drivability are formed on the same support substrate. Thecrystal grain size (high electron and positive hole mobility) iscontrolled in the polycrystalline semiconductor layer with solid phasedeposition at 600˜650° C. for 10˜15 hours, and is formed in the displayelement after forming the amorphous semiconductor layer, stratifying thepolycrystalline semiconductor layer by ion implantation or by ion dopingthe polycrystalline semiconductor layers of the display area withselectively with one of group IV elements (Si, Ge, tin and the leadetc.) for Si with polycrystalline constitution elements, in the exampleof 1×10²¹ atoms/cc or more (for example, filling the dose quantity, etc.of SiF₄ etc. 30K e V, 1×10¹⁵ Atoms/cm²). With this, you can obtain ahigh intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities by attachingthe backings after separating the support substrate from the poroussemiconductor layer and dividing the assembly into each ultra slimelectrooptic display device unit. Furthermore, you can obtain apolycrystalline SiTFT of high quality with high carrier mobilitybecause, for example, when the polycrystalline Si layer with controlscrystal grain size, contains at least a total of one of group IVelements such as Ge, tin and lead in the proper quantity (for example1×10¹⁸˜1×10²⁰ atoms/cc) with this solid phase growth, it decreases theirregularity which exists in the grain boundary of the polycrystallineSi layers and also decreases that film stress.

The manufacturing process for the twenty fourth ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 6˜10, 14˜16 and 20˜22, a process to form thepolycrystalline semiconductor layer where the crystal grain size iscontrolled by solid phase deposition after selective ion implantation orion doping with at least one kind of group IV elements such as silicon,tin, germanium and lead to the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer in the display area, a process toform the display element on the polycrystalline semiconductor layer ofthe display area where the crystal grain size is controlled, and theperipheral circuit on the monocrystalline semiconductor layer of theperipheral circuit area.

With this manufacturing method, in the aforementioned claim 6˜10, 14˜16and 20˜22, the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer is formed in the display area, and themonocrystalline semiconductor layer is formed in the peripheral circuitarea with plasma CVD, heat CVD, sputtering and evaporation. Thepolycrystalline semiconductor TFT display element which has relativelycontrolled high electron and positive hole mobility and low electriccurrent leakage qualities and the monocrystalline semiconductor TFTperipheral circuit which has high electron and positive hole mobilityand high drivability are formed on the same support substrate becausethe polycrystalline semiconductor layer on which the crystal grain size(high electron and positive hole mobility) is controlled by the solidphase deposition of 600˜650° C. for 10˜15 hours, is formed in thedisplay element after ion implantation or ion doping the amorphoussemiconductor layer or the amorphous or the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer of thedisplay area selectively with group IV elements (Si, Ge, tin and thelead etc.) for Si with polycrystalline constitution elements, in theexample of 1×10²¹ atoms/cc or more (for example, filling the dosequantity, etc. of SiF₄ etc. 30K e V, 1×10 ¹⁵ Atoms/cm²). With this, youcan obtain a high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities byattaching the backings after separating the support substrate from theporous semiconductor layer and dividing the assembly into each ultraslim electrooptic display device unit. Furthermore, you can obtain apolycrystalline SiTFT of high quality with high carrier mobilitybecause, for example, when the polycrystalline Si layer with controlscrystal grain size, contains at least a total of one of group IVelements such as Ge, tin and lead in the proper quantity (for example1×10¹⁸˜1×10²⁰ atoms/cc) with this solid phase growth, it decreases theirregularity which exists in the grain boundary of the polycrystallineSi layers and also decreases that film stress.

The manufacturing process for the twenty fifth ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 1˜5 and 11˜13 and 17˜In 19, a process to form thepolycrystalline semiconductor layers, which controls the crystal grainsize by re-crystallizing the polycrystalline semiconductor layer of thedisplay area, and processes to form the display element in thepolycrystalline semiconductor layer where the crystal grain size iscontrolled in the display area and to form a peripheral circuit area inthe monocrystalline semiconductor layer of the peripheral circuit area.

With to this production method, in the aforementioned claim 1˜5, 11˜13and 17˜19, the monocrystalline semiconductor layer is formed in theperipheral circuit area and polycrystalline semiconductor layer isformed in the display area with semiconductor epitaxial growth. Exposingto the polycrystalline semiconductor layer in the display areaselectively, Xe flash lamp annealing or pulse condition or Continuouswave laser annealing with for example the excimer laser, the opticalharmonic irregularity with the nonlinear optics effect or/and the nearultraviolet radiation laser, the visible optical laser or the infraredray laser etc., or by condensing lamp annealing for example irradiatingvia an ultraviolet lamp, the visual optical lamp and the infrared raylamp, etc. and by re-crystallizing with melting, semi-melting or heatingand cooling of the non-melted circumstance, it forms a polycrystallinesemiconductor layer which has controlled crystal grain size, in thedisplay element. It is possible to form a polycrystalline semiconductorTFT display element which has arbitrarily controlled low high electronand positive hole mobility and low electric current leakage qualities,and the monocrystalline semiconductor TFT peripheral circuit with highdrivability with high electron and positive hole mobility on the samesupport substrate. With this, you can obtain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities by attaching the backings after separating thesupport substrate from the porous semiconductor layer and dividing theassembly into each ultra slim electrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

The manufacturing process for the twenty sixth ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 6˜10 and 14˜16 and 20˜22, a process to formpolycrystalline semiconductor layers which control the crystal grainsize by re-crystallizing the amorphous semiconductor layer of thedisplay area or the amorphous and polycrystalline mixture semiconductorlayers or the polycrystalline semiconductor layers, and a process toform the peripheral circuitry in the monocrystalline semiconductor layerof the peripheral circuit area and the display element in thepolycrystalline semiconductor layer which controls crystal grain size,in the display area.

With this production method, the aforementioned claim 1˜5, 11˜13 and17˜19, the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layers or polycrystallinesemiconductor layer in the display area and the monocrystallinesemiconductor layer in the peripheral circuit area are formed. Theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerin the display area are selectively exposed with Xe flash lamp annealingor pulse conditioning or Continuous wave laser annealing, for examplewith excimer laser, the optical harmonic irregularity with the nonlinearoptics effect or/and the near ultraviolet radiation laser, the visibleoptical laser and the infrared ray laser etc., or by condensing lampannealing for example irradiating with an ultraviolet lamp, the visualoptical lamp and the infrared ray lamp, etc. and by re-crystallizingwith melting, semi-melting or heating and cooling of the non-meltedcircumstance, it forms a polycrystalline semiconductor layer in whichthe crystal grain size is controlled in the display element. It ispossible to form a polycrystalline semiconductor TFT display elementwhich has arbitrarily controlled low high electron and positive holemobility and low electric current leakage qualities, and themonocrystalline semiconductor TFT peripheral circuit with highdrivability with high electron and positive hole mobility on the samesupport substrate. With this, you can obtain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities by attaching the backings after separating thesupport substrate from the porous semiconductor layer and dividing theassembly into each ultra slim electrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

The manufacturing process for the twenty seventh ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 1˜5, 11˜13 and 17˜19, a process to form thepolycrystalline semiconductor layer which controls crystal grain size byre-crystallizing the display area after ion implantation or the iondoping selectively with a minimum of one kind of group IV elements suchas silicon, tin, germanium and lead to the polycrystalline semiconductorlayers of the display area, and a process to form the peripheralcircuitry in monocrystalline semiconductor layer of the peripheralcircuit area and the display element in the polycrystallinesemiconductor layer of the peripheral circuit area.

With this manufacturing method, the aforementioned claim 1˜5, 11˜13 and17˜19, the polycrystalline semiconductor layer is formed in the displayarea by semiconductor epitaxial growth and the monocrystallinesemiconductor layer is formed in the peripheral area. After ionimplantation on or ion doping selectively with at least one kind ofgroup IV elements such as silicon, tin, germanium and lead, for examplewith Si ion 1×10²¹ atoms/cc or more, (for example SiF₄ etc. 30K e V,1×10¹⁵ atoms/cm²) to the polycrystalline semiconductor in the displayarea and by selectively exposing to the polycrystalline semiconductorlayer in the display area mentioned before by Xe flash lamp annealing,or pulse conditioning or Continuous wave laser annealing, for examplewith excimer laser, the optical harmonic irregularity with the nonlinearoptics effect or/and the near ultraviolet radiation laser, the visibleoptical laser or the infrared ray laser etc., or by condensing lampannealing for example irradiating via an ultraviolet lamp, the visualoptical lamp and the infrared ray lamp, etc. and by re-crystallizingwith melting, semi-melting or heating and cooling of the non-meltedcircumstance, it forms a polycrystalline semiconductor layer which hascontrolled crystal grain size, in the display element. It is possible toform a polycrystalline semiconductor TFT display element which hasarbitrarily controlled low high electron and positive hole mobility andlow electric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit with high drivability with highelectron and positive hole mobility on the same support substrate. Withthis, you can obtain a high intensity, high definition and sophisticatedultra slim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities byattaching the backings after separating the support substrate from theporous semiconductor layer and dividing the assembly into each ultraslim electrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

The manufacturing process for the twenty eighth ultra slim electroopticdisplay device unit in this invention includes as follows;

in the aforementioned claim 6˜10, 14˜16 and 20˜22, which controlscrystal grain size by re-crystallizing the display area after ionimplantation or the ion doping selectively with a minimum of one kind ofgroup IV elements such as silicon, tin, germanium and lead to thepolycrystalline semiconductor layers of the display area, and a processto form the peripheral circuitry in monocrystalline semiconductor layerof the peripheral circuit area and the display element in thepolycrystalline semiconductor layer of the peripheral

With this manufacturing method, the aforementioned claim 6˜10, 14˜16 and20˜22, the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer are formed in the display area and themonocrystalline semiconductor layer is formed in the peripheral area.After ion implantation and ion doping selectively with at least one kindof group IV elements such as silicon, tin, germanium and lead, forexample the Si ion 1×10²¹ atoms/cc or more, (for example SiF₄, etc. 30KeV, 1×10¹⁵ atoms/cm²) to the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor in the display area, and by exposing theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer or the polycrystalline semiconductor layerin the display area mentioned before selectively with Xe flash lampannealing or pulse conditioning or Continuous wave laser annealing, forexample with excimer laser the optical harmonic irregularity with thenonlinear optics effect or/and the near ultraviolet radiation laser, thevisible optical laser or the infrared ray laser etc., or by condensinglamp annealing for example irradiating via an ultraviolet lamp, thevisual optical lamp and the infrared ray lamp, etc. and byre-crystallizing with melting, semi-melting or heating and cooling ofthe non-melted circumstance, it forms a polycrystalline semiconductorlayer which has controlled crystal grain size, in the display element.It is possible to form a polycrystalline semiconductor TFT displayelement which has arbitrarily controlled low high electron and positivehole mobility and low electric current leakage qualities, and themonocrystalline semiconductor TFT peripheral circuit with highdrivability with high electron and positive hole mobility on the samesupport substrate. With this, you can obtain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities by attaching the backings after separating thesupport substrate from the porous semiconductor layer and dividing theassembly into each ultra slim electrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

The manufacturing process for the twenty ninth ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 1˜5, 11˜13 and 17˜19, a process to form both thepolycrystalline semiconductor layers, which contains at least one kindof group IV elements such as tin, germanium and lead with semiconductorepitaxial growth in the display area, and the monocrystallinesemiconductor layer which does not include the group IV elements, in theperipheral circuit area, a process to form the polycrystallinesemiconductor layers which control the crystal grain size with the solidphase growing the polycrystalline semiconductor layer of the displayarea, a process to both form the display elements on the polycrystallinesemiconductor layer, with controlled crystal grain size in the displayarea and the peripheral circuitry on the monocrystalline semiconductorlayer of the display area.

According to this manufacturing method, the aforementioned claim 1˜5,11˜13 and 17˜19, the polycrystalline semiconductor layer which containsat least one kind of group IV elements such as tin, germanium and leadis formed in the display area with semiconductor epitaxial growth, and amonocrystalline semiconductor layer which does not include group IVelements if formed in the aforementioned peripheral circuit area. It ispossible to form a polycrystalline semiconductor TFT display elementwhich has arbitrarily controlled low high electron and positive holemobility and low electric current leakage qualities, and themonocrystalline semiconductor TFT peripheral circuit with highdrivability with high electron and positive hole mobility on the samesupport substrate, because the display element is formed on thepolycrystalline semiconductor layer, which controls crystal grain sizein the display area, and the peripheral circuit in the monocrystallinesemiconductor layer of the peripheral area. And by separating thesupport substrate from the deformative area of the porous semiconductorlayer and the ion implantation layer and attaching the backing togetherand then by dividing the assembly into each ultra slim electroopticdisplay device unit, With this, you can obtain a high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities.

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

The manufacturing process for the thirtieth ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 1˜5, 11˜13 and 17˜19, a process to form thepolycrystalline semiconductor layers which contains at least 1 kind ofthe group IV elements such as tin, germanium and lead with semiconductorepitaxial growth in the display area and the monocrystallinesemiconductor layer which does not contain group IV elements in theperipheral circuitry, a process to form a polycrystalline semiconductorlayer where the crystal grain size is controlled by re-crystallizing thepolycrystalline semiconductor layer in the display area, a process toform the display area in the polycrystalline semiconductor layers whichcontrol crystal grain size of the display area and the peripheralcircuit area in the monocrystalline semiconductor layer of theperipheral circuit area.

With this production method, the aforementioned claim 1˜5, 11˜13 and17˜19, the polycrystalline semiconductor layer which contains at leastone kind of the group IV elements such as tin, germanium and lead withthe semiconductor epitaxial growth, is formed and the monocrystallinesemiconductor layer which does not contain group IV elements in theperipheral circuit area. In the display area of the polycrystallinesemiconductor layer where the crystal grain size is controlled and byre-crystallizing with melting, semi-melting or heating and cooling ofthe non-melted circumstance, by exposing with Xe flash lamp annealing orpulse conditioning or continuous wave laser annealing, for example, withexcimer laser, the optical harmonic irregularity with the nonlinearoptics effect or/and the near ultraviolet radiation laser, the visibleoptical laser or the infrared ray laser etc., or by condensing lampannealing for example irradiating via an ultraviolet lamp, the visualoptical lamp and the infrared ray lamp, etc. selectively, to thepolycrystalline semiconductor layer in the display area It is possibleto form a polycrystalline semiconductor TFT display element which hasarbitrarily controlled low high electron and positive hole mobility andlow electric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit with high drivability with highelectron and positive hole mobility on the same support substratebecause the peripheral circuit is formed on the monocrystallinesemiconductor layer of the peripheral area. With this, you can obtain ahigh intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities by attachingthe backings after separating the support substrate from the poroussemiconductor layer and dividing the assembly into each ultra slimelectrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

The manufacturing process for the thirty first ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 6˜10, 14˜16 and 20˜22, a process to form theamorphous semiconductor layer which contains at least one kind of groupIV elements such as tin, germanium and lead, or the amorphous andpolycrystalline mixture semiconductor layers or the polycrystallinesemiconductor layers in the display area, and the monocrystallinesemiconductor layer in the peripheral circuit area, a process to form apolycrystalline semiconductor layer where the crystal grain size iscontrolled which is done with selective solid phase deposition on theamorphous semiconductor layer in the display area or the amorphous andthe polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer, and a process to form the display element in thepolycrystalline semiconductor layer of the display area where thecrystal grain size is controlled and the peripheral circuitry in themonocrystalline semiconductor layer of the peripheral circuit area.

With this manufacturing method, the aforementioned claim 6˜10, 14˜16 and20˜22, the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer which contains at least one kind of the group IVelements such as tin, germanium and lead, etc., is formed in the displayarea, and the monocrystalline semiconductor layer is formed in theperipheral circuit area. The polycrystalline semiconductor layer, wherethe crystal grain size is controlled by the solid phase growth, theamorphous semiconductor layer of the display area or the amorphous andthe polycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer are formed. It is possible to form a polycrystallinesemiconductor TFT display element which has arbitrarily controlled lowhigh electron and positive hole mobility and low electric currentleakage qualities, and the monocrystalline semiconductor TFT peripheralcircuit with high drivability with high electron and positive holemobility on the same support substrate because the peripheral circuit isformed on the monocrystalline semiconductor layer of the peripheral areabecause the display element is formed in the polycrystallinesemiconductor layer of the display area where the crystal grain size iscontrolled and the peripheral circuitry in the monocrystallinesemiconductor layer of the peripheral circuit area. With this, you canobtain a high intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities by attachingthe backings after separating the support substrate from the poroussemiconductor layer and dividing the assembly into each ultra slimelectrooptic display device unit.

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

The manufacturing process for the thirty second ultra slim electroopticdisplay device unit in this invention includes as follows; in theaforementioned claim 6˜10, 14˜16 and 20˜22, a process to form theamorphous semiconductor layer which contains at least one kind of groupIV elements such as tin, germanium and lead, or the amorphous and thepolycrystalline mixture semiconductor layers or the polycrystallinesemiconductor layers in the display area, and the monocrystallinesemiconductor layer in the peripheral circuit area, a process to form apolycrystalline semiconductor layer where the crystal grain size iscontrolled by selectively re-crystallizing the amorphous semiconductorlayer or the amorphous and the polycrystalline mixture semiconductorlayer or polycrystalline semiconductor layer in the display area, and aprocess to form display elements in the polycrystalline semiconductorlayer where the crystal grain size is controlled and the peripheralcircuitry is formed in the monocrystalline semiconductor layer of theperipheral circuit area of the display area.

According to this manufacturing method, the aforementioned claim 6˜10,14˜16 and 20˜22, the amorphous semiconductor layer, which contains atlease one kind of group IV elements such as tin, germanium and lead, orthe amorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer are formed in the aforementioneddisplay area, and the monocrystalline semiconductor layer is formed inthe aforementioned peripheral circuit area. In the display area of thepolycrystalline semiconductor layer where the crystal grain size iscontrolled and by re-crystallizing with melting, semi-melting or heatingand cooling of the non-melted circumstance, by exposing with Xe flashlamp annealing or pulse conditioning or continuous wave laser annealing,for example, with excimer laser, the optical harmonic modulated with thenonlinear optics effect or/and the near ultraviolet radiation laser, thevisible optical laser or the infrared ray laser etc., or by condensinglamp annealing for example irradiating via an ultraviolet lamp, thevisual optical lamp and the infrared ray lamp, etc. relative to theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer of the display area. It is possible to forma polycrystalline semiconductor TFT display element which hasarbitrarily controlled low high electron and positive hole mobility andlow electric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit with high drivability with highelectron and positive hole mobility on the same support substratebecause the peripheral circuit is formed on the monocrystallinesemiconductor layer of the peripheral area. With this, you can obtain ahigh intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities by attachingthe backings after separating the support substrate from the poroussemiconductor layer and dividing the assembly into each ultra slimelectrooptic display device unit.

Meanwhile, it is possible to see improvements to the polycrystallinesemiconductor layer of the display area due to flash lamp annealing,laser annealing or condensing lamp annealing of the semiconductor activelayer for example, from the surface to a depth of 50˜200 nm (dependingon the type of fill ion and fill depth, laser type selection, etc.).

And if the polycrystalline Si film on which the crystal grain size iscontrolled by flash lamp annealing, laser annealing or condensing lampannealing, contains the proper quantity (1×10¹⁸˜1×10²⁰ atoms/cc) at aminimum of the total of one kind of group IV elements such as Ge, tinand lead, you can obtain a polycrystalline SiTFT of high quality withhigh carrier mobility because it decreases the irregularity which existsin the grain boundary of Polycrystalline Si layers and also decreasesthe film stress.

In the the 1^(st) through the 32^(nd) manufacturing methods for theelectrooptical display device unit invention mentioned above, it isdesirable to separate the support substrate from the monocrystallinesemiconductor layer after forming a groove at least to the poroussemiconductor layer or to the ion implantation layer along the divisionline that is the division boundary within the scribe line, when dividingthe assembly into each ultra slim electrooptic display device unit.

The separation of the support substrate becomes easy for the ultra slimtype or the electrooptical display element substrate layer of the ultraslim type SOI structure because of this process. Furthermore, thecracking, chipping and occurrence of cracks at the time of channelforming are prevented because the electrooptical display elementsubstrate layer of ultra slim type or ultra slim type SOI is supportedby the support substrate during the channel formation.

The separation of the porous semiconductor layer or ion implantationlayer from the deformative area after the annealing process forexfoliation can be accomplished with the injection of a high pressurejet of fluid, vapor, liquid or a mixture of vapor and liquid into thedeformative area of the ion implantation while turning the poroussemiconductor layer or after the annealing process for exfoliation. Itis very possible to separate effectively with the injection of a highpressure fluid jet of a mixture of liquid and vapor, due to the impactforce of the bubbles of vapor that develop in the fluid in a mixture ofvapor and fluid.

Now, if the high pressure fluid jet injection happens to add minuteamounts of solid matter, it is possible to effectively directly separatethe minute solid matter that collides with the porous semiconductorlayer or the deformative area of the ion implantation layer after theannealing process for exfoliation. In addition, if the high pressurefluid jet injection takes the form of ultrasonic waves, the ultrasonicvibration operates in the deformative area of ion implantation layer orthe porous semiconductor layer after the annealing process forexfoliation. Then, it is possible to more effectively separate at thedeformative area of porous semiconductor layer or ion implantation layerafter the annealing process for exfoliation.

Also, the separation from the porous semiconductor layer or the ionimplantation layer can be done with laser processing or laser water jetprocessing to the porous semiconductor layer or the ion implantationlayer while it is turning. Especially, in case where the groove isformed before the separation, it can be separated by the laserprocessing or the laser water jet processing to the porous semiconductorlayer or the ion implantation layer while it is turning, or by the highpressure fluid jet injection to the deformative area of poroussemiconductor layer or the ion implantation layer after the annealprocessing for exfoliation which is in the midst of the turning.

With the manufacturing method for the ultra slim electrooptic displaydevice unit in this invention mentioned above, an ultra slim andreflective LCD as an ultra slim electrooptic display device unit can beobtained by separating the support substrate after sealing andlaminating the facing substrate and by injecting the liquid crystalthough the specified liquid crystal gap which is formed by the displayelement and the peripheral circuit on the support substrate, and byattaching the backing to the ultra slim electrooptic display elementsubstrate after its separation and then after dividing the assembly intoeach ultra slim electrooptic display device unit.

The ultra slim reflective LCD is separated from the support substrateafter sealing and laminating the facing substrate through the specifiedliquid crystal gap on the support substrate which forms the displayelement and the peripheral circuit. The LCD is obtained by attaching thenon-defective chip of the backing to the non-defective chip inside theultra slim electrooptic display element substrate after its separationand then, dividing the assembly into each ultra slim electroopticdisplay device unit after injecting the liquid crystal.

In addition, in the production method of the ultra slim electroopticaldisplay of this invention as described above, the backings are attachedwith sealant to an ultra slim electrooptic display element substrateafter its separation, a facing substrate which has had the alignmentfilm formed on it or had alignment treatment through transparentelectrode formation, and an electrooptic display element substrate,which had the alignment treatment or alignment film formation. These aresealed and laminated through the specified liquid crystal gap. An ultraslim reflective LCD can be obtained by injecting the liquid crystal toeach ultra slim electrooptic display device unit after its division.

The ultra slim reflective LCD can be obtained with following process.The backing is attached with sealant to the ultra slim electroopticdisplay element substrate after its separation, the non-defective chipof the facing substrate which has had the alignment film formed on it orhad alignment treatment through transparent electrode formation, issealed and laminated on to the non-defective chip inside theelectrooptic display element substrate, which has had alignment filmformation and alignment treatment, through the specified liquid crystalgap. The LCD is filled and sealed with the liquid crystal for each ultraslim electrooptic display device unit after its separation, or the LCDcan be obtained by dividing the assembly into each ultra slimelectrooptic display device unit after it is injected with the liquidcrystal.

Or, the ultra slim reflective LCD can be obtained with the followingprocess. The backing is attached with sealant to the ultra slimelectrooptic display element substrate after its separation, thenon-defective chip of the facing substrate, which has had the alignmentfilm formed on it or had alignment treatment through transparentelectrode formation, and which is cut, sealed and laminated to thenon-defective chip inside the electrooptic display element substrate,which has had alignment film formation and alignment treatment throughthe specified liquid crystal gap. The LCD can be obtained by dividingthe assembly into each ultra slim electrooptic display device unit afterit is injected with the liquid crystal.

And, the ultra slim reflective LCD can be obtained with followingprocess. The non-defective chip of the facing substrate is sealedthrough the specified liquid crystal gap to the non-defective chipinside the electrooptic display element substrate of monocrystallinesemiconductor layer. After injecting the liquid crystal, the supportsubstrate is separated. Then, the backing is attached with sealant tothe inside of the ultra slim electrooptic display element substrateafter its separation. The LCD can be obtained by dividing the assemblyinto each ultra slim electrooptic display device unit.

Or, the ultra slim reflective LCD can be obtained with followingprocess. The non-defective chip of the facing substrate is sealed to thenon-defective chip inside the electrooptic display element substrate ofmonocrystalline semiconductor layer through specified liquid crystalgap. After injecting the liquid crystal, the support substrate isseparated. Then, the backing of non-defective chip is attached withsealant to the non-defective chip inside the ultra slim electroopticdisplay element substrate after its separation. The LCD can be obtainedby dividing the assembly into each ultra slim electrooptic displaydevice unit.

On the other hand, with the manufacturing method mentioned above forultra slim electrooptic display device unit of this invention, the ultraslim reflective LCD as an ultra slim electrooptic display device unitcan be obtained by removing the equivalent area to the pixel openingsection of the display area in the electrooptic display elementsubstrate by etching, and then, by planarizing the surface of thisremoved area with an optically transparent material. The transparentelectrode which connects to the pixel display element is formed on topof this. The electrooptic display element substrate, which has hadalignment layer formation and orientation treatment, is laminated andsealed to the facing substrate which has had the alignment layerformation and orientation treatment forming the transparent electrode,through the specified liquid crystal gap. The support substrate isseparated and the transparent backing is attached to the ultra slimelectrooptic display element with transparent sealant unit after itsseparation. The LCD is obtained by injecting the liquid crystal afterdividing the assembly into each ultra slim electrooptic display deviceunit.

With the manufacturing method mentioned above of ultra slim electroopticdisplay device unit in this invention, the ultra slim reflective TYPELCD as an ultra slim electrooptic display device unit can be obtained byremoving the equivalent area to the pixel opening section of the displayarea in the electrooptic display element substrate by etching, and then,planarizing the surface of this removed area with an opticallytransparent material. The transparent electrode which connects to thepixel display element is formed on top of this. The electrooptic displayelement substrate, which has had alignment layer formation andorientation treatment, is laminated and sealed to the facing substrate,which has had the alignment layer formation and orientation treatmentforming the transparent electrode, through the specified liquid crystalgap. The support substrate is separated, and the non-defectivetransparent backing chip is attached with transparent sealant to thenon-defective chip of the ultra slim electrooptic display element unitafter its separation. The LCD is obtained by injecting the liquidcrystal after dividing the assembly into each ultra slim electroopticdisplay device unit.

Or, the ultra slim reflective TYPE LCD can be obtained with thefollowing process. The equivalent part to the pixel opening section ofthe display area in the electrooptic display element substrate isremoved by etching, and the surface of this removed area is planarizedwith an optically transparent material. The transparent electrode whichconnects to the pixel display element is formed on top of this, thenon-deformative chip of the facing substrate, which has had alignmentlayer formation and orientation treatment by forming the transparentelectrode which connects to the pixel display element on top of it, tothe non-deformative chip inside the electrooptic display elementsubstrate, which has had alignment layer formation and orientationtreatment, are laminated and sealed through the specified liquid crystalgap. After that, the liquid crystal is injected and then, the supportsubstrate is separated. A minimum optical of the transparent material ofthe pixel opening section of the display area is exposed and thetransparent support s attached with transparent sealant to the ultraslim electrooptic display device unit after its separation. The LCD isobtained by injecting the liquid crystal after dividing the assemblyinto each ultra slim electrooptic display device unit.

Or, the ultra slim reflective TYPE LCD can be obtained with thefollowing process. The equivalent area to the pixel opening section ofthe display area in the electrooptic display element substrate isremoved by etching, and the surface of this removed area is planarizedwith an optically transparent material. The transparent electrode whichconnects to the pixel display element is formed on top of this. Thenon-defective chip of the facing substrate which has had alignment layerformation and alignment treatment by forming transparent electrode issealed to the non-deformative chip inside the electrooptic displayelement substrate which is has had alignment layer formation andalignment treatment through the specified liquid crystal gap. Afterthat, the LCD is injected with liquid crystal and then, separated fromthe support substrate. A minimum of the optical transparency material ofthe pixel opening section of the display area is exposed and it attacheswith transparent sealant to the non-defective chip of transparentsupport to the non-defective chip which is inside the ultra slimelectrooptic display device unit after its separation. Then, the LCD canbe obtained by dividing the assembly into each ultra slim electroopticdisplay device unit.

And the ultra slim transmissive type LCD can be obtained as follows. Bysealing and laminating the non-defective chip inside the electroopticdisplay element substrate that has had alignment layer formation andorientation treatment, to the non-defective chip of the facing substratewhich has had alignment layer formation and orientation treatment bytransparent electrode formation. It is injected with the liquid crystalthrough the specified liquid crystal gap, and the support substrate isseparated. The transparent backing is attached with transparent sealantinside the ultra slim electrooptic display element substrate after itsseparation by dividing the assembly into each ultra slim electroopticdisplay device unit.

Or, the ultra slim transmissive type LCD can be obtained as follows. Bysealing and laminating the non-defective chip inside the electroopticaldisplay element substrate that has had alignment layer formation andorientation treatment, to the non-defective chip of the facing substratewhich has had alignment layer formation and orientation treatment bytransparent electrode formation. It is injected with the liquid crystalthrough the specified liquid crystal gap, and the support substrate isseparated. The transparent backing is attached with transparent sealantinside the ultra slim electrooptic display element substrate after itsseparation by dividing the assembly into each ultra slim electroopticdisplay device unit.

Also, ultra slim transmissive type LCD of this invention mentioned abovecan be obtained with the manufacturing method for ultra slimelectrooptic display device unit as follows. After attaching thetransparent backing with transparent sealant to the ultra slimelectrooptic display element substrate after its separation, theequivalent area to the pixel opening section of display area ofelectrooptic display element substrate is removed by etching. Thesurface of the removed area is planarized with an optically transparentmaterial, forming the clear electrode which is connected to pixeldisplay element. The electrooptic display element substrate which hashad alignment layer formation and orientation treatment, and the facingsubstrate which has had alignment layer formation and orientationtreatment, are laminated and sealed through the specified liquid crystalgap. Then, the LCD can be obtained by dividing the assembly into eachultra slim electrooptic display device unit.

Also, ultra slim transmissive type LCD can be obtained as follow. Afterattaching a transparent backing with transparent sealant to the ultraslim electrooptic display element substrate after its separation, theequivalent area to the pixel opening section of the display area of theelectrooptic display element substrate is removed by etching. Thesurface of the removed area is planarized with an optically transparentmaterial, forming the clear electrode which is connected to the pixeldisplay element, the non-defective chip inside the electrooptic displayelement substrate which has had alignment layer formation andorientation treatment, and the non-defective chip of the facingsubstrate which has had alignment layer formation and orientationtreatment. It is then cut, are laminated and sealed through thespecified liquid crystal gap. Then, the LCD can be obtained by injectingthe liquid crystal into each ultra slim electrooptic display device unitafter dividing or by dividing the assembly into each ultra slimelectrooptic display device unit after injecting the liquid crystal.

Or, ultra slim transmissive type LCD can be obtained as follows. Afterattaching a transparent backing with transparent sealant to the ultraslim electrooptic display element substrate after its separation, theequivalent area to the pixel opening section of the display area of theelectrooptic display element substrate is removed by etching. Thesurface of the removed area is planarized with an optically transparentmaterial, forming the clear electrode which is connected to the pixeldisplay element, the non-defective chip of the electrooptic displayelement substrate which has had alignment layer formation andorientation treatment, and the non-defective chip of the facingsubstrate which has had alignment layer formation and orientationtreatment. This is cut, laminated and sealed through the specifiedliquid crystal gap. Then, the LCD can be obtained by injecting theliquid crystal.

Also, for super thin transmissive type LCD, by attaching with alight-resistant transparent sealant to the separated super thinelectrooptical display element substrate and the transparent substrate,for example, glass without an antireflective film with an opticalquality of rectilinear transmissivity of 80% or more and with at least 1(W/m*K) of thermal conductivity, for instance, quartz glass andtransparent crystallized glass (neoceram, CLEARCERAM, Zerodur, etc.)etc., furthermore, glass without an antireflective film, and with anoptical quality of rectilinear transmissivity of 80% or more and with atleast 10 (W/m*K) of thermal conductivity, for example highlytransmissive ceramic polycrystalline substances {crystalline oxidescreated by electromelting or sintering of MgO (magnesia), Y₂O₃(yttrium),CaO (Calcium Oxide), AL₂O₃(Monocrystalline sapphire), BeO (beryllia),polycrystalline sapphires, etc., monocrystalline or polycrystalline ofdouble oxide crystalline YAG (Yttrium Aluminum Garnet), monocrystallineor polycrystalline MgAl₂O₄(Spinel), 3Al₂O₃2SiO₂Al₂O₃SiO₂ and so on}, afluoride monocrystalline body (calcium fluoride, magnesium fluoride andbarium fluoride etc.), vapor phase synthetic diamond film coated highlytransmissive ceramic polycrystalline substances, or a fluoridemonocrystalline body or transparent crystallized glass, or the crystaletc., this transmissive type LCD for projectors achieves increasedquality and reliability exhibiting high intensity, high definition andlong product life and showing the high emission scattering effectsvis-à-vis strong incident light.

In the meantime, you need to use the aforementioned thermally conductiveglass (film highly thermal conductivity) even with the facing substrate(including the micro lens substrate, the black mask substrate, etc.), adustproof glass with antireflective film formation for the incidentside, or a dustproof glass with antireflective formation for the outputside. For example, you can expect an even higher thermal radiationeffect by attaching as a structure of the monocrystalline sapphiredustproof glass of antireflective film formation with incident side, thefacing substrate of monocrystalline sapphire, liquid crystal layer,ultra slim electrooptic display element substrate, support substrate ofmonocrystalline sapphire, and monocrystalline sapphire dustproof glasswith antireflective film formation with light-resistant transparentsealant.

Furthermore, in case of a reflective type LCD for projectors, byattaching with a light-resistant transparent sealant to the transparentsubstrate, as a facing substrate material and a dustproof glass materialwith antireflective film formation on the incident side as mentionedabove, for example glass without an antireflective film with an opticalquality of rectilinear transmissivity of 80% or more and with at least 1(W/m*K) of thermal conductivity, for instance, quartz glass andtransparent crystallized glass (neoceram, CLEARCERAM, Zerodur, etc.)etc., furthermore glass without an antireflective film, and with anoptical quality of rectilinear transmissivity of 80% or more and with atleast 10 (W/m*K) of thermal conductivity, for example highlytransmissive ceramic polycrystalline substances {crystalline oxidescreated by electromelting or sintering of MgO (magnesia), Y₂O₃(yttrium),CaO (Calcium Oxide), AL₂O₃(Monocrystalline sapphire), BeO (beryllia),polycrystalline sapphires, etc., monocrystalline or polycrystalline ofdouble oxide crystalline YAG (Yttrium Aluminum Garnet), monocrystallineor polycrystalline MgAl₂O₄(Spinel), 3Al₂O₃₂SiO₂Al₂O₃SiO₂ and so on}, afluoride monocrystalline body (calcium fluoride, magnesium fluoride andbarium fluoride etc.), vapor phase synthetic diamond film coated highlytransmissive ceramic polycrystalline substances, or a fluoridemonocrystalline body or transparent crystallized glass, or the crystaletc., This LCD achieves increased quality and reliability exhibitinghigh intensity, high definition and long product life and showing thehigh emission scattering effects vis-à-vis strong incident light.

Furthermore, for example, as a structure of the double refraction freemonocrystalline which forms an antireflective film on the incomingradiation side or YAG polycrystalline or dustproof glass of spinel,monocrystalline or polycrystalline YAG and the facing substrate ofspinel, liquid crystal layer, ultra slim electrooptic display elementsubstrate, metallic support substrate, it is expected to have high heatdiffusion effect by attaching the monocrystalline or polycrystallinewhich formed the antireflective film, and the dust proof glass of spineland monocrystalline or polycrystalline YAG and the facing substrate ofspinel, and attaching the ultra slim electrooptic display elementsubstrate and metallic support substrate with the high thermalconductivity and conductivity sealant.

By the way, after injecting the liquid crystal and sealing by laminatingthe facing substrate with the micro lens array formation which functionsas the condenser lens and has a transparent electrode and has had thealignment layer formation and the alignment process, and the ultra slimelectrooptic display element substrate, which has the transparentelectrode which connects to the display element and alignment layerforming and orientation treatment by etching the pixel opening sectionof the display area and by embedding and planarizing the surface with anoptically transparent material, the support substrate is separated fromthe deformative area of the porous semiconductor layer and the ionimplantation layer. The reminder of the exfoliation is etched asrequired and an optically transparent material is exposed. The ultraslim electrooptic display element substrate, which has an opticallytransparent material exposed through the insulating layer, and thetransparent support substrate, is attached with transparent sealant,forming a micro lens array, which functions as a field lens, and makes adual micro lens structure. With this, you can obtain a transmissive typeLCD for the projector with higher intensity, high definition and longlife because this dual micro lens structure can raise the effectivenumerical aperture of the pixel to the highest degree by raising theutilization efficiently of available light and by condensing the doublemicro lens function which gives a higher accuracy when compared to theformer dual micro lens structure.

Furthermore, after the injecting the liquid crystal and sealing bylaminating the facing substrate with the micro lens array formation,which has the reflective film formed around each micro lens and whichfunctions as the condenser lens which has had the transparent electrodeand the alignment layer formation and alignment processing, and theultra slim electrooptic display element substrate, which has thetransparent electrode, which connects to the display element, and hashad the alignment layer forming and orientation treatment by etching thepixel opening section of the display area and by embedding andplanarizing the surface with an optically transparent material, thesupport substrate is separated from the deformative area of the poroussemiconductor layer and the ion implantation layer. The reminder of theexfoliation is etched as required and an optically transparent materialis exposed. The ultra slim electrooptic display element substrate, whichhas an optically transparent material exposed through the insulatinglayer, and the transparent support substrate, is attached withtransparent sealant, forming a micro lens array, which functions as afield lens, and makes a dual micro lens structure. With this, you canobtain a transmissive type LCD for the projector with higher intensity,high definition and long life because this dual micro lens structure canraise the effective numerical aperture of the pixel to the highestdegree by raising the utilization efficiently of available light and bycondensing the double micro lens function which gives a higher accuracywhen compared to the former dual micro lens structure.

By the way, it is possible to improve the picture quality by removingthe monocrystalline semiconductor layer of the pixel opening section ofthe display area by forming both the insulating film and thelight-shielding metallic film in order and by embedding and planarizingthe surface with an optically transparent material, and depending on thelight shielding action of the opaque metal film because it can prevent aleak light to the display element due to the strong incident light,especially in case of black type metallic film with low reflectivecharacteristics.

You can have a transmissive type LCD for the projector which is highintensity, high definition and sophisticated by preventing the electriccurrent leak of TFT by placing the light-shielding metallic film by eachpixel opening medial wall to ground the electric potential at this timeand prevent the charge build up in each section as a result of strongincident light.

On the other hand, with the ultra slim semi-transmissive type TCD as anultra slim electrooptic display device unit, with the manufacturingmethod for the ultra slim electrooptic display device unit in thisinvention mentioned above, the suitable area of the pixel openingsection of the display area of the electrooptic display elementsubstrate is removed by etching, and the surface of the removed area isembedded and planarized with an optically transparent material.Furthermore, the two areas of the pixel electrode the reflective and thetransmissive, which connect to the pixel display element, is formedthere and the electrooptic display element substrate which has hadalignment layer formation and alignment processing, and the facingsubstrate which has had alignment layer formation and alignmentprocessing and transparent electrode formation, are laminated and sealedthrough the specified liquid crystal gap. After that, the supportsubstrate is separated, making an optically transparent material of thepixel opening section expose the display area. The transparent backingis attached with transparent sealant to the ultra slim electroopticdisplay element substrate after its separation. The LCD can be obtainedby injecting the liquid crystal after dividing the assembly into eachultra slim electrooptic display device unit. With this process, you canobtain the ultra slim semi-transparent LCD which is formed with thepixel opening section of the display part of ultra slim electroopticdisplay element substrate where the light transmittance is low and it isdifficult to transmit sufficient light with an optically transparentmaterial.

Or, with the ultra slim semi-transmissive type LCD, the suitable area tothe pixel opening section of display area of electrooptic displayelement substrate is removed by etching, and the surface of the removedarea is embedded and planarized with an optically transparent material.Furthermore, the pixel electrode of the two areas of reflective andtransmissive, which connect to the pixel display element is formedthere, and the electrooptic display element substrate which has hadalignment layer formation and the alignment process, and the facingsubstrate which has had alignment layer formation and the alignmentprocess and transparent electrode formation, are laminated and sealedthrough the specified liquid crystal gap. After that, the supportsubstrate is separated, exposing an optically transparent material ofthe pixel opening section of the display area. The non-defective chip ofthe transparent backing is attached to the non-defective chip of theultra slim electrooptic display element substrate after its separationwith transparent sealant. The LCD is obtained by injecting the liquidcrystal after dividing the assembly into each ultra slim electroopticdisplay device unit.

Or, with the ultra slim semi-transmissive type LCD, the suitable area tothe pixel opening section of display area of electrooptic displayelement substrate is removed by etching, and the surface of the removedarea is embedded and planarized with an optically transparent material.The pixel electrode of the two areas of reflective and transmissive,which connect to the pixel display element is formed there, and thenon-defective chip inside the electrooptic display element substratewhich has had alignment layer formation and the alignment process, andthe non-defective chip of the facing substrate which has had alignmentlayer formation and the alignment process and transparent electrodeformation, are laminated and sealed through the specified liquid crystalgap. Then the liquid crystal is injected. After that, the supportsubstrate is separated exposing an optically transparent material of thepixel opening section of the display area. The transparent backing isattached to the ultra slim electrooptic display element substrate afterits separation with transparent sealant. The LCD is obtained byinjecting the liquid crystal after dividing the assembly into each ultraslim electrooptic display device unit.

Or, with the ultra slim semi-transmissive TCD, the suitable area to thepixel opening section of the display area of the electrooptic displayelement substrate is removed by etching, and the surface of the removedarea is embedded and planarized with an optically transparent material.The two areas of the pixel electrode the reflective and thetransmissive, which connect to the pixel display element is formedthere, and the non-defective chip inside the electrooptic displayelement substrate, which has had alignment layer formation and thealignment process, and the non-defective chip of the facing substratewhich has had alignment layer formation and the alignment process andtransparent electrode formation, are laminated and sealed through thespecified liquid crystal gap. Then the liquid crystal is injected. Afterthat, the support substrate is separated exposing an opticallytransparent material of the pixel opening section of the display area.The non-defective chip of the transparent backing is attached withtransparent sealant to the non-defective chip inside the ultra slimelectrooptic display element substrate after its separation. The LCD isobtained by injecting the liquid crystal after dividing the assemblyinto each ultra slim electrooptic display device unit.

Or, with the ultra slim semi-transmissive TCD, the two areas of thepixel electrode the reflective and the transmissive, which connect tothe pixel display element is formed, and the non-defective chip insidethe electrooptic display element substrate which has had alignment layerformation and the alignment process, and the non-defective chip of thefacing substrate which has had alignment layer formation and thealignment process and transparent electrode formation are laminated andsealed through the specified liquid crystal gap. Then the liquid crystalis injected and the support substrate is separated. The transparentbacking is attached with transparent sealant inside the ultra slimelectrooptic display element substrate after its separation. The LCD isobtained by dividing the assembly into each ultra slim electroopticdisplay device unit.

Or, with the ultra slim semi-transmissive TCD, the two areas of thepixel electrode the reflective and the transmissive, which connect tothe pixel display element is formed, and the non-defective chip insidethe electrooptic display element substrate which has had alignment layerformation and the alignment process, and the non-defective chip of thefacing substrate which has had alignment layer formation and thealignment process and transparent electrode formation are laminated andsealed through the specified liquid crystal gap. Then the liquid crystalis injected and the support substrate is separated. The non-defectivechip of the transparent backing is attached with transparent sealant tothe non-defective chip inside the ultra slim electrooptic displayelement substrate after its separation. The LCD is obtained by dividingthe assembly into each ultra slim electrooptic display device unit.

Or, with the manufacturing method for the ultra slim electroopticdisplay device unit in this invention mentioned above, the transparentbacking is attached with transparent sealant to the ultra slimelectrooptic display element substrate after its separation. Then thesuitable area to the pixel opening section of display area ofelectrooptic display element substrate is removed by etching and thesurface of the removed area is embedded and planarized with an opticallytransparent material. Furthermore, the two areas of the pixel electrodethe reflective and the transmissive, which connect to the pixel displayelement is formed there and the electrooptic display element substratewhich has had alignment layer formation and the alignment process, andthe facing substrate which has had alignment layer formation and thealignment process and transparent electrode formation are laminated andsealed through the specified liquid crystal gap. The ultra slimsemi-transparent type LCD can be obtained by injecting the liquidcrystal after dividing the assembly into each ultra slim electroopticdisplay device unit. With this process, you can obtain the ultra slimsemi-transparent LCD which is formed with the pixel opening section ofthe display part of the ultra slim electrooptic display elementsubstrate where the light transmittance is low and it is difficult forlight to transmit sufficiently with an optically transparent material.

Or, with ultra slim semi-transmissive LCD, the transparent backing isattached with transparent sealant to the ultra slim electrooptic displayelement substrate after its separation. Then the suitable area to thepixel opening section of display area of electrooptic display elementsubstrate is removed by etching and the surface of the removed area isembedded and planarized with an optically transparent material.Furthermore, the two areas of the pixel electrode the reflective and thetransmissive, which connect to the pixel display element, are formedthere and the non-defective chip of the electrooptic display elementsubstrate which has had alignment layer formation and the alignmentprocess, and the non-defective chip of the facing substrate which hashad alignment layer formation and the alignment process and transparentelectrode formation and is cut, laminated, and sealed through thespecified liquid crystal gap. The ultra slim semi-transparent LCD can beobtained by injecting the liquid crystal after dividing the assemblyinto each ultra slim electrooptic display device unit or by dividing theassembly into each ultra slim electrooptic display device unit afterinjecting the liquid crystal.

Or, with the ultra slim semi-transmissive type LCD, the transparentbacking is attached with transparent sealant to the ultra slimelectrooptic display element substrate after its separation. Then thesuitable area to the pixel opening section of display area ofelectrooptic display element substrate is removed by etching, thesurface of the removed area is embedded and planarized with an opticallytransparent material. Furthermore, the two areas of the pixel electrodethe reflective and the transmissive, which connect to the pixel displayelement, is formed there and the non-defective chip of the electroopticdisplay element substrate which has had alignment layer formation andthe alignment process and cut, and the non-defective chip of the facingsubstrate which has had alignment layer formation and the alignmentprocess and transparent electrode formation is cut, laminated and sealedthrough the specified liquid crystal gap. The ultra slimsemi-transparent LCD can be obtained by injecting the liquid crystal.

Furthermore, with the ultra slim transmissive or semi-transmissive LCD,if the polycrystalline semiconductor layer of the display area of theultra slim electrooptic display element substrate is thin, for examplewhen it is less than 50 nm, it is not always necessary to embed with theoptically transparent material by etching the pixel opening sectiondepending on the purpose of usage. It is possible to lower the cost byattaching the transparent support substrate like it is, with thetransparent sealant.

With the manufacturing method of the ultra slim electrooptic displaydevice unit of this invention mentioned above, the cathode, the organicEl emission layer and the anode, which are connected to the pixeldisplay element of the support substrate which forms the display elementand the peripheral circuit are formed and the support substrate isseparated after sealing with a moisture proof resin. The backing isattached with a transparent sealant to the ultra slim electroopticdisplay element substrate after its separation. Then, you can obtain theultra slim surface luminous organic EL as an ultra slim electroopticdisplay device unit by dividing the assembly into each ultra slimelectrooptic display device unit.

Or, with the ultra slim surface luminous organic EL, the cathode, theorganic El emission layer and the anode which are connected to the pixeldisplay element of the support substrate which forms the display elementand the peripheral circuit, are formed and the support substrate isseparated after sealing with a moisture proof resin. The non-defectivechip of the backing is attached with transparent sealant to thenon-defective chip inside the ultra slim electrooptic display elementsubstrate after its separation. Then, you can obtain the display bydividing the assembly into each ultra slim electrooptic display deviceunit.

With the manufacturing method of the ultra slim electrooptic displaydevice unit of this invention mentioned above, the cathode, the organicEl emission layer and the anode, which are connected to the pixeldisplay element, are formed after attaching the backing with the sealantto the ultra slim electrooptic display element substrate after itsseparation. Then, you can obtain the ultra slim surface luminous organicEL as an ultra slim electrooptic display device unit by sealing with amoisture proof resin and by dividing the assembly into each ultra slimelectrooptic display device unit.

On the other hand, with manufacturing method for the ultra slimelectrooptic display device unit mentioned above in this invention, oran ultra slim underside emission organic EL as an ultra slimelectrooptic display device unit, the area which is suitable to thepixel opening section of the display area of the electrooptic displayelement substrate is removed by etching. The surface of the removed areais embedded with an optically transparent material and planarized. Theanode, the organic EL emission layer and the cathode, which areconnected to the pixel display elements are formed on the supportsubstrate which is separated after sealing with a moisture proof resin.The transparent backing is attached with sealant to the ultra slimelectrooptic display element substrate after its separation. Then, thedisplay can be obtained by dividing each ultra slim electrooptic displaydevice unit.

Or, with the ultra slim underside emission organic EL, the area which issuitable to the pixel opening section of the display area of theelectrooptic display element substrate is removed by etching. Thesurface of the removed area is embedded with an optically transparentmaterial and planarized. The anode, the organic EL emission layer andthe cathode, which are connected to the pixel display elements areformed on the support substrate which is separated after sealing with amoisture proof resin. The non-defective chip of the transparent backingis attached with sealant to the non-defective chip inside the ultra slimelectrooptic display element substrate after its separation. Then, thedisplay can be obtained by dividing each ultra slim electrooptic displaydevice unit.

On the other hand, in the manufacturing method for ultra slimelectrooptic display device unit in this invention mentioned above, withthe ultra slim underside emission organic EL, the transparent backing isattached with transparent sealant to the ultra slim electrooptic displayelement substrate after its separation, the area which is suitable tothe pixel opening section of the display area of the electroopticdisplay element substrate is removed by etching. The surface of theremoved area is embedded with an optically transparent material andplanarized. The anode, the organic EL emission layer and the cathode,which are connected to the pixel display elements, are formed on that,Then, the display can be obtained by sealing with a moisture proof resinand by dividing the assembly into each ultra slim electrooptic displaydevice unit.

With the ultra slim reflective LCD and the surface luminous organic Elyou can achieve an ultra slim electrooptic display device unit which hashigh intensity, high definition, is sophisticated and highly affordableby forming a part of the peripheral circuitry including the memorycircuit, etc. other than the display circuit in the monocrystallinesemiconductor layer under the reflective electrode of the pixel display.

In addition, you can achieve the ultra slim electrooptic display deviceunit which has high intensity, high definition, is sophisticated andhighly affordable by forming the peripheral circuitry and the displaycircuit or the peripheral circuits of the multi layer wiring structurein the monocrystalline semiconductor layer.

Furthermore, you can achieve lower cost by increasing the good quantityper wafer due to the shrinking of the LCD panel by forming theperipheral circuit in the monocrystalline semiconductor layer of thesealing area.

By the way, unlike the grating constant of the monocrystalline Si layer,for example, the silicon germanium mixture crystalline layer (calledSiGe layer from now on) of the distortion impression semiconductor whichimpresses the distortion in the aforementioned monocrystalline Si layeris formed on the porous Si layer. It creates an insulating layer on thedisplay area after forming the insulating layer in the entire area.Then, the poly Si layer is formed on the display area with semiconductorepitaxial growth after etching the insulating layer in the peripheralcircuit area. The distortion impression semiconductor SiGe layer in theperipheral circuit area and the distortion channel layer of themonocrystalline Si layer (called the distortion Si layer from now on) inthe seed are formed, or the SiGe layer of the distortion impressionsemiconductor is formed on the monocrystalline Si substrate withsemiconductor epitaxial growth. The insulating layer is formed in theentire area and the insulating layer is left in the display area. Thepoly Si layer is formed in the display area with semiconductor epitaxialgrowth after etching the insulating layer in the peripheral area. TheSiGe layer of the distortion impression semiconductor is formed in theperipheral circuit area, the distortion Si layer of the distortionchannel layer in the seed or the SiGe layer of the distortion impressionsemiconductor on the insulating layer. The poly Si layer is formed inthe display area with Si epitaxial growth, the SiGe layer of thedistortion impression semiconductor in the peripheral circuit area andthe distortion Si layer of the distortion channel layer in the seed.With these processes, the band structure is changed by distorting thedistortion channel semiconductor layer. As a result, because thedegeneracy is alleviated and the electron scattering is controlled, theelectron mobility is raised. Because of this, it becomes possible tohave a an ultra slim electrooptic display device unit which exhibitshigh performance, high definition and high quality which consists of thedisplay part or the peripheral circuit of MOSTFT which has high electronand positive hole mobility and high drivability. For example, comparedto the monocrystalline Si layer of a non-distortion channel layer, theelectron hole mobility is approximately 1.76 times greater.

At this time, the germanium density in the distortion impressionsemiconductor layer increases from the contact surface of the porous Silayer, or from the contact surface of the monocrystalline Si substrate,or from the contact surface of the insulating layer gradually, and whenthe desired density is achieved, for example, when the Ge density equalsto 2 0˜3 0% of the gradient constitution of the distortion Si layer, theelectron mobility which is desired is substantially higher with the SiGelayer surface of the distortion impression semiconductor layer.

In the meantime, with the manufacturing method for the ultra slimelectrooptic display device unit in this invention, it is desirable tomaintain the circumstance where ultraviolet ray light hardening tape.The circumstance of the firm retention and the surface protection bythis ultraviolet ray light hardening type tape makes it possible toseparate because the ultraviolet ray lighting hardening tape has strongadhesion. Especially, when the channel forms alongside the divided lineinside the divided area, it is possible to prevent etching unevenness,breaking, and cracking etc. of the ultra slim electrooptic displayelement substrate peripheral due to the stress when separating fromseparated layer because the inside of the groove fills up and keeps itwith the ultraviolet ray lighting hardening sealant of the ultravioletray light hardening tape. In addition, the tape operates as a protectivelayer even when etching the unnecessary porous semiconductor layers andthe like. Due to this process, it is possible to prevent unevenness suchas etching unevenness, breaking, cracking, etc. of the ultra slimelectrooptic display element substrate periphery. Furthermore, becausethe tape adhesion of the ultraviolet ray light hardening tape becomeseasy to weaken and exfoliate by the light of the ultraviolet rays, it iseasy to remove the paste without leaving anything after the separation.Moreover, it is possible to receive the static electricity damage whenseparating or exfoliating because the ultraviolet ray lighting hardeningtape helps to protect and prevent this damage due to electrification.

Furthermore, it is also possible to prevent electrification through thetransfer of thermal expansion tape of exfoliation type which does nothave sealant.

By the way, it is desirable to have at least one kind of the siliconoxide film as the insulating layer which forms the SOI structure, thesilicon nitride film, the laminating film which of silicon oxide andsilicon oxy-nitride, the silicon nitride film, the laminating film whichlaminates with the silicon oxide and the silicon nitride and the siliconoxide in order, and aluminum nitride film, but its especially desirableto include the silicon nitride film. Because of this reason, it ispossible to prevent the permeation of the unnecessary elements, forexample the halogen chemical element, to the monocrystallinesemiconductor layer from the support substrate side during the formationprocess of this display element or the peripheral circuit to themonocrystalline semiconductor layer. And it is possible to prevent themonocrystalline semiconductor layer from receive the bad influences, forexample curvature strain, of thermal expansion in the poroussemiconductor layer which forms in the support substrate during theformation process of this display element and the peripheral circuit.

Moreover, when the monocrystalline semiconductor layer and the poroussemiconductor layer under the insulating layer in the SOI structureafter the separation is etched, you can obtain an ultra slimelectrooptic display element substrate of the ultra slim SOI structurewhich does not have unevenness upon etching because the unevenness actsas a etching stopper.

With the manufacturing process of the ultra slim electrooptic displaydevice unit in this invention, after removing the polycrystallinesemiconductor layer of the pixel opening section in the display area orthe amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer, the embedded surface isleveled with an optically transparent material after forming a minimumof the insulating layer and the light shielding metallic film. By covingthe side section or the top and the side of the polycrystallinesemiconductor layer or the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer whichforms the display element area with the light-shielding metallic filmthrough the insulating film, the image quality is improved. Because itprevents a light leakage to the display element by the strong incidentlight by the light shielding action of the light-shielding metallic filmand by the low reflective characteristics, especially in case of theblack metallic film.

Moreover, it is possible to prevent the build up of charge in eachsection due to strong incident light by channeling the electricpotential to the grounding light-shielding metallic film through theinsulating film and to the side or the top and the side of thepolycrystalline semiconductor which forms the display element of thedisplay area. With that, you can achieve an ultra slim transmissive typeLCD for the projector which exhibits high intensity, high definition andis sophisticated by preventing the electric current leakage in the TFT.

Furthermore, at this time, the transmissive LCD is obtained by embeddingthe optically transparent material after removing the light-shieldingmetallic film from the underneath of the pixel opening section in thedisplay area because the bottom of the pixel opening section of thedisplay area is transmissive.

By the way, the white reflective film is formed on the liquid crystalside of the facing substrate, which corresponds to the whole peripheralcircuit area and the corresponding area other than the pixel openingsection inside the display area of the ultra slim electrooptic displayelement substrate, and the black low reflective light-shielding film isformed on the surface of the transparent support substrate, whichcorresponds to the whole peripheral circuit area and the correspondingarea other than the pixel opening section of inside the display area ofthe ultra slim electrooptic display element substrate. The life of theLCD panel is extended because this raises the contrast by reflecting theunnecessary part of the strong incident light and decreases the rise inliquid crystal temperature.

Furthermore, the image quality is increased by preventing the electriccurrent leakage of the TFT and by preventing the leakage of thereflected light from the back with the black low reflectivelight-shielding film.

At this time, with the separation method for the double poroussemiconductor layer, it is desirable to make the diameter of the seedsubstrate which forms the monocrystalline semiconductor layer throughthe porous semiconductor layer slightly smaller or larger than thediameter of the support substrate which forms the monocrystallinesemiconductor layer through the porous semiconductor layer. Because ofthis, the seed substrate is separated by applying high pressure fluidjet injection or the laser water jet injection, etc to the poroussemiconductor layer from the immediate side direction or a diagonaldirection. At the same time, the support substrate will not be separatedfrom the porous semiconductor layer of the support substrate because itweakens the impact of the high pressure fluid jet injection or theinjection or the laser water jet injection, etc., to the poroussemiconductor layer of the support substrate.

Also, with the manufacturing method of separation for the double poroussemiconductor layer, it is desirable that the porous semiconductor layerwhich forms in the seed substrate has a higher porosity rate than theporous semiconductor layer which forms in the support substrate. And itis desirable that the porous semiconductor layer which forms in the seedsubstrate is thicker than the porous semiconductor layer which forms inthe support substrate.

Because of these reasons, the separation of the seed substrate can bedone securely, and we are able to ease the porosity rate and thicknessadjustment of the porous semiconductor layer of the seed substrate andthe support substrate. During the process of forming the display elementand the peripheral circuit, we can prevent damage, for example, curvedistortion or temperature expansion of the porous semiconductor layer,when the monocrystalline semiconductor layer forms on the supportsubstrate.

Etching unevenness, breaking and cracking of the ultra slim SOI layer inthe peripheral part can be prevented by doing C molding in theperipheral area in the surface of the support substrate which includesthe ultra slim SOI layer after separating the seed substrate, and, notonly for the aforementioned separation method for the double poroussemiconductor layer, but also for the separation method of the doubleion implantation layer and the separation method of the porous/ionimplantation layer.

You can arbitrarily set the angle and the width of C molding, and it isdesirable to do this with the grindstone, the diamond wheel and thelaser, etc. Furthermore, it is possible to do the light etching with thehydrofluoric acid etchant to remove the Si dust and the micro cracks asrequired.

(Effect of Invention)

The effect below can be seen with this invention.

(1) The insulating layer is formed on the surface of the crystalsemiconductor layer and the insulating layer of the peripheral circuitarea is removed by leaving the insulating layer of the display area. Thepolycrystalline semiconductor layer is formed on the display area andthe monocrystalline semiconductor layer is formed on the peripheralcircuit area with semiconductor epitaxial growth. By forming the displayelement on the polycrystalline semiconductor layer of the display areawhere the crystal grain size is arbitrarily controlled (high electronand positive hole mobility) with the flash lamp annealing method or thesolid phase deposition method or the laser annealing method, etc. asrequired, and forming the peripheral circuit on the monocrystallinesemiconductor layer in the peripheral area, it is possible to form thepolycrystalline semiconductor layer TFT display element which hasrelatively low high electron and positive hole mobility that isarbitrarily controlled and exhibits low electric current leakagequalities, and the monocrystalline semiconductor TFT peripheral circuit,which has high electric positive hole mobility and high drivability,inside the same substrate. By this, the ultra slim electrooptic displaydevice unit such as the transmissive type LCD, the reflective type LCD,the semi-transmissive type LCD, the surface luminous organic EL and theundersurface luminous organic EL, etc. can be obtained. Those units arehigh intensity, high definition, and sophisticated, have high electronand positive hole mobility and low electric current leakage qualitiesand are suitable for a device that emits a strong light such as thelight from a projector, etc.

(2) The display area of the monocrystalline semiconductor layer isremoved and the insulating layer is exposed. The polycrystallinesemiconductor layer is formed on the display area and themonocrystalline semiconductor layer is formed on the peripheral circuitarea with semiconductor epitaxial growth. By forming the display elementon the polycrystalline semiconductor layer of the display area where thecrystal grain size is arbitrarily controlled (high electron and positivehole mobility) with the flash lamp annealing method or the solid phasedeposition method or the laser annealing method, etc. as required, andforming the peripheral circuit on the monocrystalline semiconductorlayer in the peripheral area, it is possible to form the polycrystallinesemiconductor layer TFT display element which has relatively low highelectron and positive hole mobility that is arbitrarily controlled andexhibits low electric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit, which has high electric positivehole mobility and high drivability, inside the same substrate. By this,the ultra slim electrooptic display device unit such as the transmissivetype LCD, the reflective type LCD, the semi-transmissive type LCD, thesurface luminous organic EL and the undersurface luminous organic EL,etc. can be obtained. Those units are high intensity, high definition,and sophisticated, have high electron and positive hole mobility and lowelectric current leakage qualities and are suitable for a device thatemits a strong light such as the light from a projector, etc.

(3) The display area of the monocrystalline semiconductor layer isremoved and the insulating layer is exposed. And the metallic opaquelayer is formed in the TFT display element formation area inside thedisplay area and is covered with an insulating layer on top of it. Thepolycrystalline semiconductor layer is formed on the display area andthe monocrystalline semiconductor layer is formed on the peripheralcircuit area with semiconductor epitaxial growth. By forming the displayelement on the polycrystalline semiconductor layer of the display areawhere the crystal grain size is arbitrarily controlled (high electronand positive hole mobility) with the flash lamp annealing method or thesolid phase deposition method or the laser annealing method, etc. asrequired, and forming the peripheral circuit on the monocrystallinesemiconductor layer in the peripheral area, it is possible to form thepolycrystalline semiconductor layer TFT display element which hasrelatively low high electron and positive hole mobility that isarbitrarily controlled and exhibits low electric current leakagequalities, and the monocrystalline semiconductor TFT peripheral circuit,which has high electric positive hole mobility and high drivability,inside the same substrate. By this, the ultra slim electrooptic displaydevice unit such as the transmissive type LCD, the reflective type LCD,the semi-transmissive type LCD, the surface luminous organic EL and theundersurface luminous organic EL, etc. can be obtained. Those units arehigh intensity, high definition, and sophisticated, have high electronand positive hole mobility and low electric current leakage qualitiesand are suitable for a device that emits a strong light such as thelight from a projector, etc.

(4) With aforementioned (5)˜(7), after de-crystallizing thepolycrystalline semiconductor layer by injecting with one of group IVelements (Si, Ge, tin and the lead, etc.), for example, injecting Geselectively only in the polycrystalline semiconductor layer in theaforementioned display area, the polycrystalline semiconductor layerwhich is has controlled crystal grain size (high electron and positivehole mobility) is formed in the display element with the solid phasedeposition method. The polycrystalline semiconductor TFT displayelement, which has arbitrarily controlled high electron and positivehole mobility and low electric current leakage qualities, and themonocrystalline semiconductor TFT peripheral circuit, which has highelectron and positive hole mobility and high drivability are formed onthe same support substrate. The display element of the polycrystallinesemiconductor layer with high carrier mobility and high quality can beobtained because the irregularity which exists in the crystal grainboundary of the polycrystalline semiconductor layer with the processmentioned above, and the film stress is decreased. And with this, theultra slim electrooptic display device unit such as the transmissivetype LCD, the reflective type LCD, the semi-transmissive type LCD, thesurface luminous type organic EL and the undersurface luminous typeorganic EL, etc. can be obtained by attaching the backing afterseparating the support substrate and dividing the assembly into eachultra slim electrooptic display device unit. Those units are highintensity, high definition, and sophisticated, have high electron andpositive hole mobility and low electric current leakage qualities andare suitable for a device which emits a strong light such as a lightfrom a projector, etc.

(5) The insulating layer and the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer are formed on the surface of themonocrystalline semiconductor layer with plasma CVD, heat CVD,sputtering, evaporation, etc. At a minimum, the amorphous semiconductorlayer of the peripheral circuit area or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer are removed and the amorphous semiconductor layer inthe display area or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer, and themonocrystalline semiconductor layer in the peripheral area are eachformed. By forming the display element in the polycrystallinesemiconductor layer or the amorphous semiconductor layer or theamorphous and the polycrystalline mixture semiconductor layer where thecrystal grain size is arbitrarily controlled (high electron and positivehole mobility) with the flash lamp annealing method or the solid phasedeposition method or the laser annealing method, etc. as required, andforming the peripheral circuit in the monocrystalline semiconductorlayer in the peripheral area, it is possible to form the polycrystallinesemiconductor layer TFT display element which has relatively low highelectron and positive hole mobility that is arbitrarily controlled andexhibits low electric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit, which has high electric positivehole mobility and high drivability, inside the same substrate. By this,the ultra slim electrooptic display device unit such as the transmissivetype LCD, the reflective type LCD, the semi-transmissive type LCD, thesurface luminous organic EL and the undersurface luminous organic EL,etc. can be obtained. Those units are high intensity, high definition,and sophisticated, have high electron and positive hole mobility and lowelectric current leakage qualities and are suitable for a device thatemits a strong light such as the light from a projector, etc.

(6) The display area of the monocrystalline semiconductor layer isremoved and the insulating layer is exposed. And the insulating layerand the amorphous semiconductor layer or the amorphous and thepolycrystalline mixture semiconductor layer or the polycrystallinesemiconductor layer is formed with plasma CVD, heat CVD, sputtering,evaporation, etc. At a minimum, the amorphous semiconductor layer of theperipheral circuit area or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer areremoved and the amorphous semiconductor layer in the display area or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer, and the monocrystallinesemiconductor layer in the peripheral area are each formed. By formingthe display element in the polycrystalline semiconductor layer or theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer where the crystal grain size is arbitrarilycontrolled (high electron and positive hole mobility) with the flashlamp annealing method or the solid phase deposition method or the laserannealing method, etc. as required, and forming the peripheral circuitin the monocrystalline semiconductor layer in the peripheral area, it ispossible to form the polycrystalline semiconductor layer TFT displayelement which has relatively low high electron and positive holemobility that is arbitrarily controlled and exhibits low electriccurrent leakage qualities, and the monocrystalline semiconductor TFTperipheral circuit, which has high electric positive hole mobility andhigh drivability, inside the same substrate. By this, the ultra slimelectrooptic display device unit such as the transmissive type LCD, thereflective type LCD, the semi-transmissive type LCD, the surfaceluminous organic EL and the undersurface luminous organic EL, etc. canbe obtained. Those units are high intensity, high definition, andsophisticated, have high electron and positive hole mobility and lowelectric current leakage qualities and are suitable for a device thatemits a strong light such as the light from a projector, etc.

(7) The display area of the monocrystalline semiconductor layer isremoved and the insulating layer is exposed. The light shieldingmetallic layer in the pixel display element formation area inside thedisplay area is formed. And the insulating layer and the amorphoussemiconductor layer or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer areformed in the entire area with plasma CVD, heat CVD, sputtering,evaporation, etc. At a minimum, the amorphous semiconductor layer of theperipheral circuit area or the amorphous and the polycrystalline mixturesemiconductor layer or the polycrystalline semiconductor layer areremoved and the amorphous semiconductor layer in the display area or theamorphous and the polycrystalline mixture semiconductor layer or thepolycrystalline semiconductor layer, and the monocrystallinesemiconductor layer in the peripheral area are each formed. By formingthe display element in the polycrystalline semiconductor layer or theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer where the crystal grain size is arbitrarilycontrolled (high electron and positive hole mobility) with the flashlamp annealing method or the solid phase deposition method or the laserannealing method, etc. as required, and forming the peripheral circuitin the monocrystalline semiconductor layer in the peripheral area, it ispossible to form the polycrystalline semiconductor layer TFT displayelement which has relatively low high electron and positive holemobility that is arbitrarily controlled and exhibits low electriccurrent leakage qualities, and the monocrystalline semiconductor TFTperipheral circuit, which has high electric positive hole mobility andhigh drivability, inside the same substrate. By this, the ultra slimelectrooptic display device unit such as the transmissive type LCD, thereflective type LCD, the semi-transmissive type LCD, the surfaceluminous organic EL and the undersurface luminous organic EL, etc. canbe obtained. Those units are high intensity, high definition, andsophisticated, have high electron and positive hole mobility and lowelectric current leakage qualities and are suitable for a device thatemits a strong light such as the light from a projector, etc.

(8) With aforementioned (5)˜(7), after ion filling or ion doping with atleast one kind of the group IV elements (Si, Ge, tin and the lead, etc.)selectively only to the amorphous semiconductor layer of theaforementioned display area or the amorphous and the polycrystallinesemiconductor layer or the polycrystalline semiconductor layer, thedisplay element is formed in the polycrystalline semiconductor layer orthe amorphous semiconductor layer or the amorphous and thepolycrystalline semiconductor layer which is arbitrarily controlled withthe flash lamp annealing method or the or the laser annealing method,etc. according to the needs, and the peripheral circuit is formed in themonocrystalline semiconductor layer in the peripheral area. With theseprocesses, the polycrystalline semiconductor layer TFT or the amorphoussemiconductor TFT or the amorphous and the polycrystalline mixturesemiconductor TFT display element which has relatively low high electronand positive hole mobility that is arbitrarily controlled and lowelectric current leakage qualities, and the monocrystallinesemiconductor TFT peripheral circuit, which has high electric positivehole mobility and high drivability are formed on the same substrate.

Then, the polycrystalline semiconductor TFT with high carrier mobilityand high quality is obtained because the irregularity which exists inthe crystal grain boundary of the polycrystalline semiconductor isdecreased, and the film stress is decreased. And, the backings areattached after separating the support substrate and each ultra slimelectrooptic display device units are divided form the assembly. Withthis, the ultra slim electrooptic display device unit such as thetransmissive type LCD, the reflective type LCD, the semi-transmissivetype LCD, the surface luminous type organic EL and the undersurfaceluminous type organic EL, etc. can be obtained. Those units are highintensity, high definition, and sophisticated, have high electron andpositive hole mobility and low electric current leakage qualities andare suitable for a device which emits a strong light such as a lightfrom a projector, etc.

(9) The peripheral circuit, which includes the memory circuit, is formedon the monocrystalline semiconductor layer, which is under thereflective electrode of the pixel display part, or the peripheralcircuit is formed on the monocrystalline semiconductor layer of the sealarea. Furthermore, the degree of location of the peripheral circuitinside the LCD panel is raised by forming the peripheral circuit of themultiple layer wiring structure in the monocrystalline semiconductorlayer. And, by taking the external peripheral IC function in, increasedfunctionality and reduced costs are achieved.

(10) Differing from the grating constant of the monocrystalline Si layerdescribed above, the SiGe layer of the distortion impressionsemiconductor, which impresses the distortion in the aforementionedmonocrystalline Si layer is formed on the porous Si layer, an insulatinglayer is formed in the entire area while leaving the insulating layer inthe display area. Then, the poly Si layer is formed on the display areawith semiconductor epitaxial growth after etching the insulating layerin the peripheral circuit area. The distortion impression semiconductorSiGe layer in the peripheral circuit area and the distortion channellayer of the monocrystalline Si layer (called the distortion Si layerfrom now on) in the seed are formed, or the SiGe layer of the distortionimpression semiconductor is formed on the monocrystalline Si substratewith semiconductor epitaxial growth. The insulating layer is formed inthe entire area and the insulating layer is left in the display area. Apoly-Si layer is formed in the display area with semiconductor epitaxialgrowth. The SiGe layer of the distortion impression semiconductor in theperipheral circuit area and the distortion Si layer of the distortionchannel layer in the seed are formed, and after etching the SiGe layerof the display area, the insulating layer is exposed. The poly Si layeris formed in the display area with Si epitaxial growth, the SiGe layerof the distortion impression semiconductor in the peripheral circuitarea and the distortion Si layer of the distortion channel layer in theseed. With these processes, the band structure is changed by distortingthe distortion channel semiconductor layer. As a result, because thedegeneracy is alleviated and the electron scattering is controlled, theelectron mobility is raised. Because of this, it becomes possible tohave a an ultra slim electrooptic display device unit which exhibitshigh performance, high definition and high quality which consists of thedisplay part or the peripheral circuit of MOSTFT which has high electronand positive hole mobility and high drivability. For example, comparedto the monocrystalline Si layer of a non-distortion channel layer, theelectron hole mobility is approximately 1.76 times greater.

At this time, the germanium density in the distortion impressionsemiconductor layer increases from the contact surface of the porous Silayer, or from the contact surface of the monocrystalline Si substrate,or from the contact surface of the insulating layer gradually, and whenthe desired density is achieved, for example, when the Ge density equalsto 20˜30% of the gradient constitution of the distortion Si layer, theelectron mobility which is desired is substantially higher with the SiGelayer surface of the distortion impression semiconductor layer.

(11) By separating the support substrate where the circumstance of thefacing substrate and the support substrate are maintained by theultraviolet ray light hardening type tape which does not have anysealant left and which is antistatic, the facing substrate and thesupport substrate are kept strong. Also, the surface circumstance of thefacing substrate and the support substrate are protected while they areseparated. It is possible to increase the yield and the productivitybecause the ultraviolet ray lighting hardening type tape can be removedeasily by UV light hardening with no paste remaining after theseparation. In addition, it is possible to prevent the specialdeformative occurrence with static electricity damage of thepolycrystalline semiconductor TFT circuit and the monocrystallinesemiconductor TFT circuit on the support substrate when separating,because the ultraviolet ray lighting hardening type tape has thefunction of preventing electrification. In addition, the tape operatesas a protective layer even when etching the unnecessary poroussemiconductor layers and the like. Due to this process, it is possibleto prevent unevenness such as etching unevenness, breaking, cracking,etc. of the ultra slim electrooptic display element substrate periphery.

(12) In each manufacturing method, the separation of the supportsubstrate becomes easier because the TFT substrate layer which isseparated from the support substrate, is already divided by doing theseparation of the support substrate after forming the groove along withthe dividing line, when each electrooptic display device unit isdivided, from the monocrystalline semiconductor layer at least to theporous semiconductor layer or the ion implantation layer. Because ofthis, it is possible to prevent the occurrence etching unevenness,breaking, cracking, when each ultra slim electrooptic display deviceunit is divided. Especially, because the inside the groove is filledwith the ultraviolet ray lighting hardening type sealant when the grooveis formed, it is possible to prevent the etching unevenness, breaking,cracking, etc. of the ultra slim electrooptic display element substrateperiphery because of stress when separating from the separation layer.

Or, when we divide each ultra slim electrooptic display device unit,etching unevenness, breaking, cracking can be prevented at the time ofdivision, because this can be done with the circumstance of beingattached to the substrate.

(13) After removing the polycrystalline semiconductor layer or theamorphous semiconductor or the amorphous and the polycrystalline mixturesemiconductor, the insulating film and the light-shielding metallic filmare formed in order and the optically transparent material is embedded.The picture quality is improved because light leakage from the displayelement TFT due to the strong incident light can be prevented due to thelow reflectivity with the black type metallic film, especially with thelight-shielding action of the light-shielding metallic film.

At that time, you can obtain an electrooptical display which is highintensity, high definition and sophisticated by preventing TFT electriccurrent leakage of the display element because charge build up in eachsection due to strong incident light can be prevented by leaving thelight block metallic film inside each pixel opening section and on thetop of the TFT, etc. to ground the electric potential.

(14) The transmissive type LCD with high transmissive factors can beobtained because the optically transparent material, which has hightranslucency such as transparent resin, glass, SiO₂, etc., is embeddedto the pixel opening section of the monocrystalline semiconductor layerin the display area with the optically transparent material, which isthe ultraviolet light proof.

(15) When the monocrystalline semiconductor layer and the poroussemiconductor layer are etched and where the insulating film and thelight-shielding metallic film are set in the lower part of the embeddedsection with the optically transparent material, the light transmittancerate can be kept high by not decreasing the translucency of thismaterial because the optically transparent material is not damaged bythe etching liquid.

(16) Decreased cost is possible because the seed substrate and thesupport substrate which is separated can be used again.

(17) By including the silicon nitride film in the insulation layer,unevenness caused by etching is prevented because this silicon nitridefilm functions as a stopper when it is etching after separation of thesubstrate. Also, during the time of LCD assembly and semiconductordevice processing, the permeation of element that would causedeterioration in quality, for example halogen elements, in thesemiconductor layer (polycrystalline semiconductor layer andmonocrystalline semiconductor layer) forming on the support substrateside can be prevented. Furthermore, during semiconductor deviceprocessing, distortion with curvature of the semiconductor layer can bedecreased or prevented due to the influence received from the expansionof the porous layer which was formed on the support substrate. This canlead to yield and quality.

Also, when there is an insulating layer of the silicon nitride film inthe ultra slim SOI structure after the separation, the etchingunevenness, cracking, or breaking, etc. of the ultra slim electroopticdisplay element substrate layer can be prevented due to the highrigidity.

(18) With each of the manufacturing methods, by separating the supportsubstrate after forming the groove along with the dividing line insidethe dividing area when each ultra slim electrooptic display device unitsarea divided from monocrystalline semiconductor layer to a minimum ofthe distortion area of the porous semiconductor layer or the ionimplantation layer, it becomes easy to separate the support substratewith such as high pressure fluid jet injection exfoliation method orlaser processing exfoliation method or laser water jet processingexfoliation method, etc., because the electrooptic display elementsubstrate layer of ultra slim SOI layer structure or ultra slimmonocrystalline semiconductor layer which is separated from supportsubstrate is already divided. For these reasons, it is possible toprevent the occurrence of etching unevenness, cracking, or breaking ineach ultra slim-shaped electrooptic display device unit. This leads toyield and quality improve and lowering of the cost.

Especially, when the groove is formed, the ultraviolet ray lightinghardening type sealant fills up the inside, etching unevenness,cracking, or breaking, of the ultra slim electrooptic display elementsubstrate peripheral caused by the stress when separating from theseparated layer can be prevented.

(19) With the separation method for the double porous semiconductorlayer, by making the diameter of the seed substrate which formsmonocrystalline semiconductor layer via the porous semiconductor layerslightly smaller or larger than the diameter of support substrate whichforms the monocrystalline semiconductor layer through the poroussemiconductor layer, the support substrate does not separate because thehigh pressure fluid jet injection does not hit the porous semiconductorlayer of the support substrate directly when the seed substrate isseparated by the high pressure fluid jet injection hitting the poroussemiconductor layer of the seed substrate from immediate side directionor from a slanted direction.

Furthermore, with the manufacturing method of separation for the doubleporous semiconductor layer, it is desirable to have the poroussemiconductor layer which forms on the seed substrate have a higherporosity rate than the porous semiconductor layer which forms on thesupport substrate. Also, it is desirable to have the poroussemiconductor layer which forms on the seed substrate thicker than theporous semiconductor layer which forms on the support substrate.

Because of this process, separation of the seed substrate can be donemore surely and the porosity rate and thickness adjustment of the poroussemiconductor layer of the support substrate can be modified. During theformation process of the display area and the peripheral circuit,adverse effects such as receiving the strain on the curve, or thermalexpansion of the porous semiconductor layer which forms on themonocrystalline semiconductor layer of the support substrate can beprevented.

(20) The transmissive type LCD for the projector with the ultra slimelectrooptic display element substrate which is ultraviolet light proof,which has high light transmittance, can be achieved because theoptically transparent material that is ultraviolet light proof isembedded in a material with high light transmittance rate such astransparent resin, glass, SiO₂, etc. onto the pixel opening section ofthe polycrystalline semiconductor layer or the display area or theamorphous semiconductor layer or the amorphous and the polycrystallinemixture semiconductor layer.

(21) By attaching with a light-resistant transparent sealant to theseparated super thin electrooptical display element substrate and thetransparent substrate, for example, glass without an antireflective filmwith an optical quality of rectilinear transmissivity of 80% or more andwith at least 1 (W/m*K) of thermal conductivity, for instance, quartzglass and transparent crystallized glass (neoceram, CLEARCERAM, Zerodur,etc.) etc., furthermore, glass without an antireflective film, and withan optical quality of rectilinear transmissivity of 80% or more and withat least 10 (W/m*K) of thermal conductivity, for example highlytransmissive ceramic polycrystalline substances {crystalline oxidescreated by electromelting or sintering of MgO (magnesia), Y₂O₃(yttrium),CaO (Calcium Oxide), AL₂O₃(Monocrystalline sapphire), BeO (beryllia),polycrystalline sapphires, etc., monocrystalline or polycrystalline ofdouble oxide crystalline YAG (Yttrium Aluminum Garnet), monocrystallineor polycrystalline MgAl₂O₄ (Spinel), 3Al₂O₃₂SiO₂Al₂O₃SiO₂ and so on}, afluoride monocrystalline body (calcium fluoride, magnesium fluoride andbarium fluoride etc.), vapor phase synthetic diamond film coated highlytransmissive ceramic polycrystalline substances, or a fluoridemonocrystalline body or transparent crystallized glass, or the crystaletc., this transmissive type LCD for projectors achieves increasedquality and reliability exhibiting high intensity, high definition andlong product life and showing the high emission scattering effectsvis-à-vis strong incident light.

In the meantime, you need to use the aforementioned thermally conductiveglass (film highly thermal conductivity) even with the facing substrate(including the micro lens substrate, the black mask substrate, etc.), adustproof glass with antireflective film formation for the incidentside, or a dustproof glass with antireflective formation for the outputside. For example, you can expect an even higher thermal radiationeffect by attaching as a structure of the monocrystalline sapphiredustproof glass of antireflective film formation with incident side, thefacing substrate (including the micro lens substrate, the black masksubstrate, etc.) of monocrystalline sapphire, liquid crystal layer,ultra slim electrooptic display element substrate, support substrate ofmonocrystalline sapphire, and monocrystalline sapphire dustproof glasswith antireflective film formation with light-resistant transparentsealant.

Furthermore, in case of a reflective type LCD for projectors, byattaching with a light-resistant transparent sealant to the transparentsubstrate, as a facing substrate material and a dustproof glass materialwith antireflective film formation on the incident side as mentionedabove, for example glass without an antireflective film with an opticalquality of rectilinear transmissivity of 80% or more and with at least 1(W/m*K) of thermal conductivity, for instance, quartz glass andtransparent crystallized glass (neoceram, CLEARCERAM, Zerodur, etc.)etc., furthermore glass without an antireflective film, and with anoptical quality of rectilinear transmissivity of 80% or more and with atleast 10 (W/m*K) of thermal conductivity, for example highlytransmissive ceramic polycrystalline substances {crystalline oxidescreated by electromelting or sintering of MgO (magnesia), Y₂O₃(yttrium),CaO (Calcium Oxide), AL₂O₃(Monocrystalline sapphire), BeO (beryllia),polycrystalline sapphires, etc., monocrystalline or polycrystalline ofdouble oxide crystalline YAG (Yttrium Aluminum Garnet), monocrystallineor polycrystalline MgAl₂O₄(Spinel), 3Al₂O₃₂SiO₂Al₂O₃SiO₂ and so on}, afluoride monocrystalline body (calcium fluoride, magnesium fluoride andbarium fluoride etc.), vapor phase synthetic diamond film coated highlytransmissive ceramic polycrystalline substances, or a fluoridemonocrystalline body or transparent crystallized glass, or the crystaletc., This LCD achieves increased quality and reliability exhibitinghigh intensity, high definition and long product life and showing thehigh emission scattering effects vis-à-vis strong incident light.

Furthermore, for example, as a structure of the double refraction freemonocrystalline which forms an antireflective film on the incomingradiation side or YAG polycrystalline or dustproof glass of spinel,monocrystalline or polycrystalline YAG and the facing substrate ofspinel, liquid crystal layer, ultra slim electrooptic display elementsubstrate, metallic support substrate, it is expected to have high heatdiffusion effect by attaching the monocrystalline or polycrystallinewhich formed the antireflective film, and the dust proof glass of spineland monocrystalline or polycrystalline YAG and the facing substrate ofspinel, and attaching the ultra slim electrooptic display elementsubstrate and metallic support substrate with the high thermalconductivity and conductivity sealant.

(22) The dual micro lens structure is attached to the transparentsupport substrate which forms the micro lens array which functions as afield lens, and to the ultra slim electrooptic display element substratewhich has high accuracy and thick film and which layers the facingsubstrate with the formed micro lens array which functions as acondensing lens, and has three functions; a function to condense lightwith the double micro lens function which has a higher accuracy than thedual micro lens structures in the past, a function to raise theutilization efficiency of illuminant light and a function to raise theeffective aperture rate of the pixel to the highest degree. For thesereasons, the transmitted type LCD for the projector which has highintensity, high definition and is sophisticated, can be achieved withthe ultra slim electrooptic display element substrate.

(23) The dual micro lens structure is attached to the transparentsupport substrate, which forms the micro lens array forming the lowreflective light-shielding film with a black mask function around eachmicro lens which functions as a field lens, and to the ultra slimelectrooptic display element substrate which has high accuracy and thickfilm and which layers the facing substrate with the formed micro lensarray which functions as a condensing lens, and has three functions; afunction to condense light with the double micro lens function which hasa higher accuracy than the dual micro lens structures in the past, afunction to raise the utilization efficiency of illuminant light and afunction to raise the effective aperture rate of the pixel to thehighest degree. For these reasons, the transmissive type LCD for theprojector which has high intensity, high definition and issophisticated, can be achieved with the ultra slim electrooptic displayelement substrate.

(24) The ultra slim electrooptic display device unit such as ultra slimLCD (transmissive type, semi-transmissive type and reflective type) andsurface luminous type organic EL or underside luminous type organic EL,etc. can be achieved because the display element of the ultra slimpolycrystalline semiconductor TFT or the amorphous semiconductor TFT orthe amorphous and the polycrystalline mixture semiconductor TFT, and theultra slim monocrystalline semiconductor TFT peripheral circuit can beformed inside the same substrate as an ultra slim electrooptic displayelement substrate by laminating the facing substrate such as thetransparent glass and the resin film for example 100 μm, furthermore byattaching the support substrate such as the transparent glass and theresin film for example 100 μm.

(25) A head mount type ultra slim electrooptic display device unit whichis like a watch, a business card, a card, a glass and stamp can beobtained by using the transmissive type LCD reflective type LCD, thesemi-transmissive type LCD, the surface luminous type organic EL, theunderside luminous type organic EL, etc. which has direct vision typeand ultra slim type that is mentioned above, for instance, the ultraslim electronics product, ultra small and ultra light weight devicessuch as ultra slim digital still camera, ultra slim digital moviecamera, ultra slim acoustic equipment (CD, MD, etc.), ultra slimcellular phone, ultra slim portable television, ultra slim televisionmonitor, etc. Furthermore, you can achieve a product for data or for theAV (Audio Visual) for a projector LCD product which is ultra slim, microminiature and ultra light weight with transmissive type or reflectiveLCD which has high intensity, high definition and is sophisticated.

BRIEF DESCRIPTION OF THE DRAWINGS

(FIG. 1)

This cross section diagram shows the manufacturing process for atransmissive type LCD with the porous Si layer method of separation.

(FIG. 2)

This cross section diagram shows the manufacturing process for atransmissive type LCD with the porous Si layer method of separation.

(FIG. 3)

This cross section diagram shows the manufacturing process for atransmissive type LCD with the porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 4)

This cross section diagram of the display area shows the manufacturingprocess for a transmissive type LCD with the porous Si layer method ofseparation.

(FIG. 5)

This cross section diagram of the display area shows the manufacturingprocess for a transmissive type LCD with the porous Si layer method ofseparation.

(FIG. 6)

This cross section diagram of the display area shows the manufacturingprocess for a transmissive type LCD with the porous Si layer method ofseparation.

(FIG. 7)

This cross section diagram of the display area shows the manufacturingprocess for a transmissive type LCD with the porous Si layer method ofseparation.

(FIG. 8)

This cross section diagram shows the manufacturing process for atransmissive type LCD with the porous Si layer method of separation.

(a) This diagram shows the entire substrate.

(b) This diagram shows the display area.

(FIG. 9)

This cross section diagram shows the manufacturing process for atransmissive type LCD with the porous Si layer method of separation.

(a) This diagram shows the entire substrate.

(b) This diagram shows the display area.

(FIG. 10)

This cross section diagram shows the transmissive type LCD which isproduced by the porous Si layer method of separation.

(a) This diagram shows the transmissive type LCD in case of “without”the light-shielding film.

(b) This diagram shows the transmissive type LCD in case of “with”light-shielding film.

(FIG. 11)

This cross section diagram shows the manufacturing process for areflective type LCD with the porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 12)

This cross section diagram shows the manufacturing process for areflective type LCD with the porous Si layer method of separation.

(FIG. 13)

This cross section diagram shows a reflective type LCD which is producedby the porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 14)

This cross section diagram shows a semi-transmissive type LCD which isproduced by the porous Si layer method of separation.

(a) This diagram shows a semi-transmissive type LCD where the reflectiveelectrode with an optimal roughness was formed on the transparentelectrode.

(b) This diagram shows a semi-transparent type LCD where the transparentelectrode was formed on the reflective electrode of optimal roughness.

(FIG. 15)

This cross section diagram shows an underside emitter type organic ELwhich is produced by the porous Si layer method of separation.

(FIG. 16)

This cross section diagram shows a surface emitter type organic EL whichis produced by the porous Si layer method of separation.

(FIG. 17)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(FIG. 18)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(FIG. 19)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(FIG. 20)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(a) This diagram shows an example of forming SiO₂ as an insulatinglayer.

(b) This diagram shows an example of forming SiO₂Si₃N₄ and SiO₂ as aninsulating layer.

(FIG. 21)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(FIG. 22)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 23)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 24)

This cross section diagram shows a transmissive type LCD formed by thedouble porous Si layer method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 25)

This cross section diagram of a display area shows a transmissive typeLCD by the double porous Si layer method of separation.

(FIG. 26)

This cross section diagram shows a reflective type LCD formed by thedouble porous Si layer method of separation.

(FIG. 27)

This cross section diagram shows a transmissive type LCD formed by thehydrogen ion implantation method of separation.

(FIG. 28)

This cross section diagram shows a transmissive type LCD formed by thehydrogen ion implantation method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 29)

This cross section diagram of a display area shows the transmissive typeLCD formed by the hydrogen ion implantation method of separation.

(FIG. 30)

This cross section diagram of a display area shows the transmissive typeLCD formed by the hydrogen ion implantation method of separation.

(FIG. 31)

This cross section diagram area shows a transmissive type LCD formed bythe double hydrogen ion implantation method of separation.

(FIG. 32)

This cross section diagram area shows a transmissive type LCD formed bythe double hydrogen ion implantation method of separation.

(FIG. 33)

This cross section diagram area shows a transmissive type LCD formed bythe double hydrogen ion implantation method of separation.

(FIG. 34)

This cross section diagram area shows a transmissive type LCD formed bythe double hydrogen ion implantation method of separation.

(a) This diagram shows the display area.

(b) This diagram shows the peripheral circuit area.

(FIG. 35)

This cross section diagram of the display area shows a transmissive typeLCD formed by the double hydrogen ion implantation method of separation.

(FIG. 36)

This cross section diagram of the display area shows a transmissive typeLCD formed by the double hydrogen ion implantation method of separation.

(FIG. 37)

This cross section diagram of the display area shows a transmissive typeLCD formed by the porous Si layer/hydrogen ion implantation method ofseparation.

(FIG. 38)

This cross section diagram of the display area shows a transmissive typeLCD formed by the porous Si layer/hydrogen ion implantation method ofseparation.

(FIG. 39)

This cross section diagram of the display area shows the transmissivetype LCD formed by the porous Si layer/hydrogen ion implantation methodof separation.

(FIG. 40)

This outline cross section shows a high pressure fluid jet injectionexfoliation unit in the form of execution presented by this invention.

(FIG. 41)

This cross section diagram shows an electrooptic display device unitformed by the double porous Si layer method of separation.

(FIG. 42)

This cross section diagram explains the C chamfering of the supportsubstrate surface peripheral section after the seed substrateseparation.

(FIG. 43)

This cross section diagram shows a transmissive type LCD for theprojector using the dual micro lens (the double micro lens) structure.

(FIG. 44)

This cross section diagram shows a transmissive type LCD or a reflectivetype LCD for the projector.

(FIG. 45)

This cross section diagram (1) shows a mounting example which uses theultra slim electrooptic display device unit in this invention for directdisplay.

(FIG. 46)

This cross section diagram (2) shows a mounting example which uses theultra slim electrooptic display device unit of this invention for directdisplay.

(FIG. 47)

This cross section diagram shows a concrete example of an ultra slimelectronics product which uses this invention.

(FIG. 48)

(A) This figure shows the assembly method of an LCD and an organic ELformed with the porous semiconductor layer method of separation.

(FIG. 49)

(B) This figure shows the assembly method of an LCD and an organic ELformed with the double porous semiconductor layer method of separation.

(FIG. 50)

(C) This figure shows the assembly method of an LCD and an organic ELformed with the ion implantation layer method of separation.

(FIG. 51)

(D) This figure shows the assembly method of an LCD and an organic ELformed with the double ion implantation layer method of separation.

(FIG. 52)

(E) This figure shows the assembly method of an LCD and an organic ELformed with the porous semiconductor layer/the ion implantation layermethod of separation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An execution form of the present invention will be described in detailbelow with reference to the accompanying diagrams for betterunderstanding of the present invention.

(A) A Method of Separating a Porous Semiconductor Layer

(A-1) Ultra Slim Transmissive Type LCD

In this execution form, a method of producing an ultra slim electroopticdisplay by separation of a porous semiconductor layer using a poroussilicon layer (hereafter referred to as “Si”) is described. FIG. 1through FIG. 16 are process diagrams for manufacturing an ultra slim LCDby separation of a porous Si layer in the preferred execution form ofthe present invention.

(1) Porous Si layers (11 a: low porous Si layer, 11 b: high porous Silayer, 11 c: low porous Si layer) are formed by anodic oxidation on amonocrystalline Si substrate 10 as a support substrate.

Initially, p-type impurities are added in an approximately boron densityof 1×10¹⁹ atoms/cm³ by a CVD method using monosilane gas or diborane gasto a p-type monocrystalline Si substrate, e.g., 12 inch in diameter and1.2 mm in thickness (resistivity: 0.01˜0.02Ω·cm)

(hereafter referred to as “a Si substrate”) 10 to form a high densitysemiconductor epitaxial growth monocrystalline Si layer with a thicknessof approximately 10 μm (corresponding to a low porous Si layer 11 a aswill be mentioned later).

On] On a surface of this high density layer, p-type impurities are addedin an approximately boron density of 5×10¹⁴ atoms/cm³ by a CVD methodusing monosilane gas or diborane gas to form a low density semiconductorepitaxial growth monocrystalline Si layer with a thickness ofapproximately 20 μm (corresponding to a high porous Si layer 11 b aswill be mentioned later).

Furthermore] Furthermore, on a surface of this low density layer, p-typeimpurities are added in an approximately boron density of 5×10¹⁹atoms/cm³ by a CVD method using monosilane gas or diborane gas to form ahigh density semiconductor epitaxial growth monocrystalline Si layerwith a thickness of approximately 10 μm (corresponding to a low porousSi layer 11 c as will be mentioned later).

In the formation of a monocrystalline Si layer by a CVD method, a vaporphase epitaxy, in addition to raw materials for hydrides such asmonosilane (SiH₄), the following raw material gases can be used: thesame raw materials for hydrides such as disilane (Si₂H₆), trisilane(Si₃H₈), and tetrasilane (Si₄H₁₀) and raw material for hydrides such asdichlorosilane (SiH₂Cl₂), trichlorisilane (SiHCl₃), and silicontetrachloride (SiCl₄). A method of forming a monocrystalline Si layer isnot limited to a CVD method, and a MBE (Molecular Beam Epitaxy) methodor a sputtering method can also be applied.

Subsequently] Subsequently, an anodic formation method is applied usinga mixed solution of a 50% hydrogen fluoride solution and ethyl alcoholat a volumetric ratio of 2:1 as an electrolyte, while a current isapplied for 5 to 10 minutes at about approximately a current density of10 mA/cm² to form low porous Si layers 11 a and 11 c with a low porosityin the high density layer and a high porous Si layer 11 b with a highporosity in the low density layer.

Since the anodic reaction of Si in the hydrogen fluoride solutionrequires positive holes for the dissolution reaction of Si in the anodicformation, it is desirable to use a p-type Si substrate which easilybecomes a porous substrate. However, the application is not limited tothis material.

If a porous layer is formed by an anodic formation method, porous layersare comprised of plural numbers of layers with different porosities. Forexample, as mentioned above, a first low porous Si layer 11 a is formedon the monocrystalline Si substrate 10 followed by the formation of ahigh porous Si layer 11 b, and a second low porous Si layer 11 c in thisorder to achieve a triple layer structure. In addition, a double layerstructure can be obtained by forming a high porous Si layer 11 b and alow porous Si layer 11 c in this order on the monocrystalline Sisubstrate 10.

In this case, the porosity ranges from 40 to 80% in the high porous Silayer 11 b, whereas the porosity in the low porous Si layers 11 a and 11c ranges from 10 to 30%. The respective thickness of plural numbers oflayers having different porosities can be adjusted arbitrarily bychanging the current density and time during the anodic formation, andkinds or concentrations of the chemical solution during the anodicformation.

Besides a monocrystalline Si substrate which is prepared as a Sisubstrate by the CZ (Czochralski) method, MCZ (Magnetic Field AppliedCzochralski) method, or FZ (Floating Zone) method, monocrystalline Sisubstrate which has been treated by hydrogen annealing on its substratesurface and an epitaxial monocrystalline Si substrate can be used. Ofcourse, instead of monocrystalline Si substrates, monocrystallinecompound semiconductor substrates such as monocrystalline SiGesubstrate, SiC substrates, GaAs substrates and InP substrates can beused.

(2) A semiconductor epitaxial growth monocrystalline Si layer 12 a is 12a is formed on the porous Si layer (a low porous Si layer 11 c) (SeeFIG. 1).

Initially, in the CVD semiconductor epitaxial growing equipment, surfacepores on the low porous Si layer 11 c are sealed for surface flatteningby pre-baking at 1000 to 1100° C. under a hydrogen atmosphere. Ahydrogen annealing treatment is carried out at an etching rate of 0.0013nm/min at 1050° C. or 0.0022 nm/min at 1100° C.

Subsequently, the temperature is lowered to 1020° C. to carry out CVDusing monosilane gas as a raw material gas to form a semiconductorepitaxial growth monocrystalline layer 12 a with a thickness ofapproximately 5 μm.

As mentioned above, in the formation of a monocrystalline Si layer by aCVD method, a vapor phase epitaxy, in addition to hydrogenation rawmaterials such as monosilane (SiH₄), the following raw material gasescan be used: same hydrogenation raw materials such as disilane (Si₂H₆),trisilane (Si₃H₈), and tetrasilane (Si₄H₁₀) and halogenation rawmaterials such as dichlorosilane (SiH₂Cl₂), trichlorisilane (SiHCl₃),and silicon tetrachloride (SiCl₄). A method of forming a monocrystallineSi layer is not limited to a CVD method, and a MBE (Molecular BeamEpitaxy) method or a sputtering method can also be applied.

(3) A SiO₂ (silicon oxide) layer 13 a with a thickness of approximately100 nm is formed as an insulating layer by thermal oxidation of asurface of a monocrystalline Si layer 12 a, and a SiO₂ layer 13 a in theperipheral circuit area is removed by etching while leaving the SiO₂layer 13 a in the display area. A polycrystalline Si layer (hereafterreferred to as a poly-Si layer) 14 with a thickness of approximately 10μm in the display area and a monocrystalline Si layer 12 b with athickness of approximately 10 μm in the peripheral circuit area areformed respectively (See FIG. 2).

Besides the silicon oxide film SiO₂ prepared by thermal oxidation, aninsulating film can be provided as a laminated film comprising of asilicon oxide film and a silicon nitride film, or a laminated filmcomprising of a silicon oxide film, a silicon nitride film, and asilicon oxide film (e.g., SiO₂; 200 nm, Si₃N₄; 50 nm and SiO₂; 200 nm)which is prepared by forming a silicon nitride film (Si₃N₄) or a siliconnitride film and a silicon oxide film on the monocrystalline Si layer 12a by vacuum thermal CVD followed by thermal oxidation. Furthermore, asilicon oxy-nitride film (SiON) can be applied.

The aforementioned insulating layer of a single layer film and multiplelayer film can be formed by a plasma CVD method, sputtering method, MBEmethod and vapor deposition method.

Because both the monocrystalline Si layer 12 b and the poly-Si layer 14are formed under the same film formation conditions in the semiconductorepitaxial growth by CVD, the crystallinity (electron and positive holemobility) of the poly-Si layer 14 in the display area can not becontrolled sufficiently if the crystallinity of the monocrystalline Silayer in the peripheral circuit area is emphasized. The peripheralcircuit section of the monocrystalline Si layer 12 b is covered with aphoto resist film and Si ions are injected with a high concentration,e.g., 30 KeV, 1˜3×10¹⁵ atoms/cm² onto the surface of the poly-Si layer14 with openings to convert the surface layer to an amorphous Si film(hereafter referred to as an amorphous Si film). After exfoliation andcleaning the photo resist film, a surface layer of the poly-Si layer 14with a controlled crystal grain size is formed by solid phase depositionby carrying out an annealing treatment for 10 to 15 hours under anitrogen gas atmosphere at 600˜650° C.

It is desirable to obtain a surface layer of the poly-Si layer 14 with athickness of 50˜100 nm wherein arbitrary electron and positive holemobility based on arbitrary crystal grain size are achieved, byadjusting the Si ion injection concentration, depth and annealingconditions.

The poly-Si is defined as an aggregate of micro crystals commonly havinga grain size of approximately 10 nm or greater. An amorphous Si filmgenerally contains a grain size of 10 nm or less and is a material thatdoes not show a crystalline orientation in the X-ray diffractionanalysis.

A surface layer of the poly-Si layer 14 with a thickness of 50˜100 nmwith an arbitrarily controlled crystal grain size is formed by selectivere-crystallization for of only the poly-Si layer 14 by flash lampannealing by flash irradiation of a Xe lamp, or pulse or continuous wavelaser annealing by irradiation by an XeCl excimer laser, one of or bothof an optical harmonic modulated far infrared UV laser and near infraredUV laser of Nd:YAG lasers, visible light lasers, and infrared laser, orcondensing lamp annealing, e.g., by irradiation using a UV lamp such asultra high pressure mercury lamp, and an IR lamp such as halogen lamps,xenon lamps and arc lamps, to proceed with heating and cooling in amelting, semi-melting or non-melting condition. It is desirable toobtain a surface layer of the poly-Si layer 14 with a thickness of50˜100 nm, with arbitrary electron and positive hole mobility using anarbitrary crystal size, by adjusting the intensity of irradiation toflash lamps, lasers or condensing lamps for re-crystallization (depthfrom the surface of the poly-Si layer and time) in such a state that aSi substrate 10 is heated to an appropriate temperature (e.g., 200˜400°C.) in order to reduce film stress.

If at least one of the group IV elements including Ge (germanium), Sn(tin), Pb (lead), is added in an proper quantity (total of 10¹⁷ ˜10²²atom/cc, preferably 10¹⁸˜10²⁰ atom/cc) to the poly-Si layer 14 by ioninjection or ion doping and re-crystallized in this state by said solidphase deposition, flash lamp annealing, pulse or continuous wave laserannealing, or condensing lamp annealing, crystallization is acceleratedas well as irregularities present in the crystalline grain field (grainboundary) of the poly-Si thin film is reduced so that the film stress isreduced and it becomes easier to obtain high quality poly-Si TFT with ahigh carrier mobility.

These group IV elements can be added to the amorphous Si film or/and thepoly-Si layer by ion injection or ion doping.

The group IV elements such as Ge and tin can be added to the amorphousSi or/and poly-Si layer and the monocrystalline Si film by mixing themas gas components with the raw material gases during the Si epitaxialgrowth by CVD, or during the film formation by plasma CVD or thermalCVD.

An amorphous Si film containing H is formed by decomposition using rawmaterial gases such as monosilane (SiH₄), disilane (Si₂H₆), trisilane(SiH₈), and SiH₂F₂, and the raw materials for hydrogenates, by a highfrequency discharge at 13.56 MHz at an ambient temperature ˜300° C. bythe plasma CVD method.

Since 600° C. is the boundary between the poly-Si and amorphous Si, anamorphous Si film without containing H can be formed by thermal CVD inthe hot wall vacuum CVD equipment at 580° C. or less.

As one of the means to increase electron mobility, an application ofstrains to the channel semiconductor layer is known. If strains areapplied to a channel semiconductor layer, its band structure changes andas a result, degeneracy is alleviated to depress electron scattering sothat the electron mobility increases. Concretely, a strain-applyingsemiconductor layer of a mixed crystalline layer made of a materialhaving a greater lattice constant than that of Si is formed on amonocrystalline Si substrate. For example, if a SiGe layer with a Geconcentration ranging from 20 to 30% is formed and a monocrystalline Silayer is formed as a channel semiconductor layer on the SiGe layer, astrained Si layer is formed due to a difference in the lattice constant.If this strained channel layer is used instead of a non-strained channellayer, the electron mobility is reported to be improved significantly byapproximately 1.76-fold when compared to the case using a non-strainedchannel layer (J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, I ED M 94-373)

For example, if a monocrystalline Si layer 12 a is formed as a strainapplying semiconductor layer which is a SiGe layer with a Geconcentration ranging from 20 to 30% and a strained Si layer 12 b isformed on its top, a MOSTFT peripheral circuit is implemented, in whichthe electron mobility is significantly improved by approximately1.76-fold when compared to the monocrystalline Si layer in theconventional non-strained channel layer. Therefore, an ultra slimelectrooptic display is implemented with high intensity, high definitionand high quality.

As a film deposition method of a SiGe layer, epitaxial [vapor phase]growing methods such as the CVD method and MBE method, liquid phasegrowing methods such as LPE (liquid phase epitaxy), and solid phasegrowing methods for poly SiGe layer or amorphous SiGe layer arecurrently known. As long as the composition ratio of Ge can becontrolled for the crystalline deposition method, other depositionmethods can be used.

As Si raw materials, the following [raw materials] are desirable:hydrogenation raw materials such as monosilane (SiH₄), disilane (Si₂H₆),trisilane (Si₃H₈), and tetrasilane (Si₄H₁₀) and halogenation rawmaterial such as dichlorosilane (SiH₂Cl₂), trichlorisilane (SiHCl₃), andsilicon tetrachloride (SiCl₄). As Ge raw materials, germanium (GeH₄),germanium tetrachloride (GeCl₄) and germanium tetrafluoride (GeF₄) aredesirable.

Mixed crystalline layers made of materials having different latticeconstants such as mixed crystalline layers containing both Si and otherelements as in SiC and SiN, Group 2 to 6 element mixed crystallinelayers as in ZnSe, or Group 3 to 5 element mixed crystalline layers asin GaAs and InP, can be used as a strained semiconductor layer in placeof the SiGe layers.

The method of improving the electron mobility by the formation of astrained semiconductor layer on the strain applying semiconductor layersuch as aforesaid SiGe layer can be used when producing semiconductordevices such as picture signal processing LSI, memory LSI, CPULSI,DSPLSI, voice signal processing LSI, CCD, CMOS sensor and BiCMOS byseparating an ultra slim semiconductor layer or ultra slim SOIsemiconductor layer.

(4) According to the general technology, an ultra slim electroopticdisplay device substrate layer (hereafter referred to as an ultra slimTFT substrate layer) is formed in by respectively forming one or both ofsemiconductor devices and semiconductor for integrated circuits such asa poly-Si TFT section 15 a (See FIG. 3(a)) and wiring as display devicesections in the surface layer with a thickness ranging from 50 to 100 nmwherein crystal grain sizes are controlled arbitrarily, in the poly-Silayer 14, a monocrystalline SiTFT section 15 b (See FIG. 3 (b)), diodes,resistors, capacitors, coils and wiring as peripheral circuit sectionsin the monocrystalline Si layer 12 b.

Since the monocrystalline Si-layer 12 b shows high electron and positivehole mobility as in the Si substrate, picture signal processingcircuits, picture quality correction circuits, memory circuits, CPU(central processing unit) circuits and DSP (digital signal processor)circuits can be incorporated as well as peripheral driving circuits.

At the same time, an external output electrode (including a solder bump)65 is formed to be connected to the peripheral circuits of the ultraslim TFT substrate layer. It is desirable to be connected to a flexibleboard or be mounted on a PCB (printed circuit board) by connecting ananisometric conductive film, connecting by ultrasonic waves, orsoldering after a LCD panel is formed. In this diagram, diodes,resistances, capacitors, coils and wirings are not shown.

When forming a bump using solder as an external output electrode, adesirable height of the bump is the thickness of the facing substrate orless.

If peripheral circuits with a multilayer wiring structure or displaysections and peripheral circuits are formed in the monocrystallinesemiconductor layer, the degree of integration is increased so that anultra slim electrooptic display can be implemented inexpensively withhigh resolution, high functionality and high quality.

Furthermore, if peripheral circuits are formed even in themonocrystalline semiconductor layer in the sealed region, the number ofunits per wafer increases due to shrinking of the LCD panel sizes andthe cost reduction will be implemented.

At this stage, it is desirable to form a groove 62 (See FIG. 7) from themonocrystalline Si layer 12 b at least till until the high porous Silayer 11 b along the division line, that is a division boundary withinthe scribe line, when being [the layer] is divided into single panels ofvarious ultra slim electrooptic displays. By forming a groove 62, theultra slim TFT substrate layer as will be discussed later is dividedwithin the scribe line so that separation from the Si substrate 10becomes easy and division in the process (12) as will be discussed latercan be performed easily.

A groove 62 is preferably formed with an arbitrary width from themonocrystalline Si layer 12 b at least till until the high porous Silayer 11 b by dry etching (plasma etching using SF₆, CF₄, Cl⁺ O₂,HBr+O₂, reverse sputter etching, etc.), wet etching (fluoric acidetchants such as HF+H₂O₂+H₂O mixed solution or HF+HNO₃+CH₃COOH mixedsolution, alkaline etchants), or mechanical processing (cutting a grooveusing a blade dicing, diamond cutter, cemented carbide cutter, andultrasonic cutter).

A transparent resin 16 which is mounted in the pixel opening section isalso mounted in the groove to be able to reduce chipping, cracking andfracturing of the insulating layer and the monocrystalline Si layer 12 bwhen being separated.

(5) The poly-Si layer 14 at the pixel opening section in the displayarea is removed by etching. Due to the masking with a photo resist otherthan the pixel opening section, [the pixel opening section can beremoved] by etching such as plasma etching using Cl⁺ O₂, HBr+O₂, SF₆,CF₄, or dry etching such as reactive etching (See FIG. 4). If desirable,a wet etching with fluoric acid can be carried out using a H₂O₂+H₂Osolution mixture or HF+HNO₃+CH₃COOH) solution mixture.

(6) A transparent insulating film with a thickness of 50˜200 nm (e.g.,SiO₂ layer 13 b, SiNx and SiO₂ laminated film, SiO₂, SiNx and SiO₂laminated film, SiON, etc.) and a light-shielding metallic film with athickness of 100˜300 nm (hereafter referred to as a metallic film) 17are formed respectively on the entire surface by CVD, sputtering orvapor deposition. Subsequently, connections of the poly-Si TFT sectionon the poly-Si layer 14 (drains, sources and gates), and the metallicfilm 17 at the bottom of the pixel opening sections are removed byplasma etching using CCl₄, or by wet etching using an acidic etchingsolution.

Since the transparent insulating film and the metallic film formed onthe peripheral circuit sections are not removed by etching, leakage ofthe strong incident light is shielded to prevent TFT current leakage.

In short, when a strong incident light enters as in the case of LCDprojectors, it is desirable to cover the areas with a light shieldingfilm besides the pixel opening sections.

Subsequently, a transparent resins 16 is embedded as a light opticallytransparent material in the pixel opening sections in the display areaand the surface is planarized by CMP (See FIG. 5). Because this metallicfilm 17 prevents TFT current leakage caused by irregular reflection of astrong incident light, a low reflective metallic film made of WSi, Ti,Cr, Mo, Mo—Ta is desirable. If the metallic film 17 on the side wall ofeach pixel opening section is grounded, this prevents it from buildingup a charge by the strong incident light in order to prevent the leakcurrent from TFT.

As measures for reducing TFT current leakage due to light leakage causedby strong incident light and as measures for improving light resistance,windows are preferably opened only at the electrode connections of thepoly-Si TFT section, leaving the metallic film 17 on the poly-Si TFTfilm so that the poly-Si TFT section is entirely covered for shieldingthe light for the top, side and bottom of the poly-Si TFT section.

A transparent resin 16 is formed on the entire surface with a thicknessof 15˜20 μm to be embedded in the pixel opening section. If desirable,the surface is planarized by CMP (chemical mechanical polishing). Thetransparent resin 16 is embedded by spin coating of a transparent resinsuch as the silicone series, urethane series and epoxy series and iscured under specific conditions, for example, by a specific heattreatment. In place of the transparent resin 16, it is possible to use aoptically transparent material such as glass films or SiO₂ films, but itis necessary to have a strong light resistance against incident UV rays.

In the case of glass films, a low temperature micro glass powder whichhas been dispersed in an organic solvent is coated to fill up the pixelopening section, and fused at an appropriate temperature, such as at500˜600° C., to form a thick glass film. Alternatively, the pixelopening section is filled up with at least one kind of the followingmaterials: SiO₂, PSG (phosphosilicate glass), BPSG (boro-phosphosilicateglass, or BSG (borosilicate glass) by CVD, or sputtering. Subsequently,the surface is planarized by a method such as CMP.

(7) A window is made in the transparent resin 16 on the poly-Si TFTsection 15 a in the display area and a transparent electrode 18 a with athickness of 130˜150 nm is formed as a pixel electrode which is made ofITO (Indium-Tin-Oxide; indium oxide.tin oxide mixed transparentconductive film) and IZO (Indium-Zinc-Oxide; indium oxide.zinc oxidemixed transparent conductive film) to form an ultra slim TFT substratelayer (See FIG. 6).

(8) A facing substrate 21 is laminated on the ultra slim TFT substratelayer on the Si substrate 10 to be sealed (See FIG. 6).

An organic alignment film material such as polyimide or polyamide iscoated on the transparent electrodes 18 a and 18 b on the ultra slim TFTsubstrate layer on the Si substrate 10 and the facing substrate 21 byspin coating, dip coating or roll coating and an alignment treatment isperformed by buff rubbing. If desirable, [the surface] is cleaned byorganic cleaning using IPA (isopropyl alcohol), in order to formrespective alignment films 20 a and 20 b. Alternatively, the alignmentfilms 20 a and 20 b can be inorganic alignment films prepared by obliquedeposition of SiOx.

A facing substrate is made of quartz glass satisfying opticalcharacteristics with a linear transmittance of 80% or greater without anantireflective film, transparent crystallized glass (Neoceram,CLEARCERAM, and Zerodur, etc.) borosilicate glass, aluminosilicateglass, microsheet glass, high transparent, heat resistant andmoisture-proof resin films. If desirable, color filters or micro lensarrays are formed. In addition, a transparent electrode is formed on theentire surface and an aligned organic or inorganic alignment film isformed at least per each chip.

For a single panel of the ultra slim TFT substrate layer of the Sisubstrate 10, a sealant 22 (See FIG. 7) and a common electrode agent(not shown) are coated. For example, a facing substrate 21 with a 12inch diameter is laid with a liquid crystal gap of 2 μm to be sealed.This is a so-called face-to-face liquid crystalline assembly {A facingsubstrate in a substrate state (face) is laid over a monocrystalline Sisubstrate 10 in the substrate state (face) to be sealed} (See FIG. 6).In this case, the liquid crystalline injection hole (not shown) is leftopen.

A sealant and a common agent can be selected from among the followingagents: light curable sealants, heat curable and light curable sealants,or UV hardening sealants, heat curable and UV hardening sealants, andheat curable sealants. From the aspects of characteristics and workingefficiency, it is desirable that both are selected from the same type.

The actual sealants and common agents are comprised of a modifiedacrylate oligomer which is the major component of sealants and commonagents and which expresses the basic characteristics after curing, anacrylate monomer for controlling viscosity of the liquids, a photoinitiator for light curing or curing of the UV hardening portions, anepoxy resin which is the major component of sealants and common agentsand which expresses the basic characteristics after curing, a curingagent for curing the epoxy resin, a filler for preventing invasion ofmoisture content from the atmosphere in the sealant (silica of thepearl), and fibers equivalent to the liquid crystalline gap.

A common agent which is coated on the common pad in the TFT substratechip contains a micro pearl of a gold-plated resin which is larger thanthe liquid crystalline gap (e.g., approximately 3 μm Φ which is largerby approximately 1 μm Φ than the liquid crystalline gap). When a TFTsubstrate chip is laid over a facing substrate chip, the micro pearl isbroken under pressure and both transparent conductive films becomeelectrically connected due to the presence of broken gold plated resin.

If there is a liquid crystal alignment film such as polyimide orpolyamide in the sealed area, it is necessary to make such an effort interms of micro pearl materials and sizes that both transparentconductive films become electrically connected via the gold plated resinafter the film is broken.

If an organic liquid crystal alignment film such as polyimide is formedin the sealed area between the TFT substrate chip or/and the facingsubstrate chip by spin coating, it is important to be packed with afiller in order to prevent the moisture content from entering from theatmosphere into the sealant and optimization of the filler packing ratiois necessary based on the LCD panel sizes. For example, in the case of 1inch size projector LCD panels, a desirable filler packing ratio rangesfrom 10 to 30%. It is generally determined by the relationships betweenease in dispense coating and the ratio of penetration of the moisturecontent.

In order to achieve electrical connection between one 1 chip in theultra slim type electrooptic display device substrate layer(monocrystalline Si layer 12) and the facing substrate 21, a commonagent containing a micro pearl of gold plated resin is coated using adispenser at least at two positions on the common pad within the onechip.

Similarly, a sealant 22 containing fibers equivalent to the liquidcrystalline gap (gap agent) is coated in the sealed area for each onechip in the ultra slim type electrooptic display device substrate layer.

In the case of a direct-viewing type, the liquid crystalline gap can besecured by scattering micro spacers on the entire screen.

Bumps formed with the resin (OCS: on chip spacer) which is equivalent tothe liquid crystalline gap can be formed in arbitrary numbers around thepixel opening sections between the facing substrate 21 and the ultraslim TFT substrate layer.

The expression of “at least for every one chip” in the ultra slim TFTsubstrate layer (monocrystalline Si layer 12) and the facing substrate21 is due to the fact that organic or inorganic alignment films 20 a and20 b can be formed on the entire surface. In this specification, wedefine that one chip of the ultra slim TFT substrate layer(monocrystalline Si layer 12) is laid over one 1 chip of the facingsubstrate 21 to form one 1 panel of LCD.

In contrast to the aforesaid face-to-face liquid crystal assembly, anon-defective chip of the facing substrate in which organic or inorganicalignment film 20 b is formed after an alignment treatment by forming atransparent electrode 18 b can be laid selectively on a non-defectivechip within the ultra slim TFT substrate layer to be sealed. This isgenerally called a face-to-face liquid crystal assembly (amonocrystalline Si substrate in the substrate state (face) is laid overa facing substrate in a chip state (single piece) to be sealed).

Since in the face-to-face liquid crystal assembly, a TFT substrate layercontaining defective chips may be laid over a facing substratecontaining defective chips to be sealed, there is a possibility thatdefective LCD panels are produced, which may increase production costs.In contrast, in the face-to-single liquid crystal assembly,non-defective facing substrate chips are selectively laid overnon-defective chips within the ultra slim TFT substrate layer to besealed so that the occurrence of defective LCD panels becomes minimal,which can reduce production costs.

(9) The Si substrate 10 and the facing substrate 21 are covered with aUV hardening tape (hereafter referred to as UV tape) 23 and the Sisubstrate 10 is separated from the high porous Si layer 11 b by a highpressure fluid jet injection exfoliation method using a water jet, airjet or water/air jet, or a laser process exfoliation method or a laserwater jet process exfoliation method (See FIG. 7). After the separatedSi substrate 10 is if desirable treated for surface re-grinding andetching, and thermally treated under the atmosphere containing hydrogen,it can be reused if desirable.

The UV tape 23 consists of a UV tape base such as polyolefin orpolyethyleneterephthalate (PET), and an antistatic acrylic UV hardeningsealant with a strong bonding strength without leaving any residual glue[after separation]. The Si substrate 10 can be separated from highporous Si layer 11 b while both facing substrate 21 and the Si Substrate10 are still firmly held and their surfaces are respectively protectedby the UV tape 23 due to a strong bonding strength of the UV hardeningsealant.

If a groove 62 is formed, the interior of the groove 62 in theface-to-single liquid crystal assembly is filled with a UV hardeningsealant of the UV tape 23. This can prevent chipping, cracking andbreaking at the peripheral area of the ultra slim TFT substrate due tothe stress applied when the layer is separated. It also acts as aprotective layer when the unwanted porous Si layer is removed by etchingto prevent chipping, cracking and breaking at the peripheral area of theultra slim TFT substrate. Furthermore, the UV hardening sealant weakensit sealant power due to irradiation of UV-rays so that the UV tape 23can be removed without leaving any residual glue after separation. Forsome usages, an antistatic thermal expansion stripping type sealant tapecan be used without leaving any residual glue after separation.

In the case of face-to-single liquid crystal assembly, it is desirableto fill the gaps sufficiently by setting the thickness of the sealant ofthe UV tape to be greater than the thickness of the facing substrate.

In order to prevent cracking, chipping and breaking due to warping whilethe substrate is held after being separated, the facing substrate 21 isbonded on one side using a two-sided UV tape and a transparent sheethaving rigidity such as glass having rigidity can be bonded on the otherside.

If desirable, in the case of a face-to-single liquid crystal assembly, aglass sheet having rigidity via wax and a metallic sheet can be bondedat least on the facing substrate 21.

In order to avoid any adverse effects of stripping and cleaning on LCDsealability, organic sealants and water soluble sealants which can beremoved by an alcoholic solvent such as ethanol and IPA (isopropylalcohol) are desirable examples of this wax.

Examples of such water soluble sealants are a hot-melt series of watersoluble solid waxes such as Aquawax 20/50/80 (Nikka Seiko K. K.: majorcomponent: fatty acid glyceride), Aquawax 553/531/442/SE (majorcomponents: polyethylene glycol, vinylpyrrolidone copolymers, glycerinpolyethers), PEG Wax 20 (major component: polyethylene glycol), etc., orwater soluble waxes such as Aqua Liquid WA-320 (Nikka Seikko K. K., asynthetic resinous liquid sealant: major components: polyethyleneglycol, vinyl pyrrolidone derivatives, methanol), WA-20511/QA-20566(major components: polyethylene glycol, vinyl pyrrolidone derivatives,IPA, water). These sealants can be cleaned after stripping with warmpure water at 50 to 60° C.

The antistatic UV tape 23 includes those having a conductive transparentfilm of ITO or IZO on the sealant surface of the UV tape base or thosewith a conductive surface chemical treatment, or those containingconductive transparent oxide micro particles (ITO or IZO) in the UVhardening sealants at such levels that the electrostatic damage can beprevented. If necessary, these can be combined. If an antistatic UV tape23 is used, the electrostatic damage in the semiconductor devices formedin the TFT substrate layer can be prevented.

Since the electrostatic break-down during the manufacturing process canbe prevented by such antistatic functions, defects in the semiconductorcharacteristics due to electrostatic damage can be prevented. Adesirable level of surface resistance of UV hardening sealants beforeand after curing is such that electrostatic damage at a level of10⁶˜10¹²Ω/m can be prevented.

When separated from the high porous Si layer 11 b, a high pressure fluidjet injection exfoliation method using water jet, air jet or water/airjet is applied. In this case, a high pressure fluid jet injectionstripping equipment used is shown in FIG. 40. FIG. 40 is an overallcross-sectional view of the high pressure fluid jet injection strippingequipment used in the execution form of the present invention.

The high pressure fluid jet injection stripping equipment shown in FIG.40 is comprised of a pair of holders 81 a and 81 b which makes asubstrate rotate by suction in vacuum in the up and down direction, anda micro nozzle 83 which ejects a high pressure fluid jet 82. A guardring stopper 80 is a cylindrical tool enclosing the holders 81 a and 81b. The guard ring stopper 80 has a slit with a diameter of 10 to 50 μm(84) so that the width of the high pressure fluid jet 82 injected from afine nozzle 83 is restricted. The diameter of the slit can be determinedby the hydraulic pressure of the high pressure fluid jet 82 and the airpressure.

In this high fluid jet injection stripping equipment, for example, asubstrate prepared by bonding a Si substrate 10 with a facing substrate21 as shown in FIG. 6 is supported between the holder 81 a and 81 b. Inthis case, a layer to be separated (separation layer) is a high porousSi layer 11 b. In FIG. 40, those other than a Si substrate 10, a porousSi layer 11 b and a facing substrate 21 are not shown in this figure forsimplicity.

The height of the guard ring stopper 80 and the heights of the Sisubstrate 10 and the facing substrate 21 which are sandwiched with theholders 81 a and 81 b are adjusted such that [the direction] of a highpressure fluid jet 82 injected from the precision nozzle 83 is preciselyadjusted to hit exactly the porous Si layer 11 b to be separated.Subsequently, the holders 81 a and 81 b are rotated so that the pressurefrom the high pressure fluid 82 injected from the precision nozzle 83acts at the high porous Si layer 11 b in order to separate the Sisubstrate 10.

Since a width of the high pressure fluid jet 82 injected from theprecision nozzle 83 is controlled by the slit hole 84 of the guard ringstopper 80 and its height is precisely adjusted to accurately hit thehigh porous Si layer 11 b to be separated, it does not hit the areasother than the high porous Si layer 11 b as strongly enough to beseparated.

The high pressure fluid jet 82 can be formed by injecting liquids suchas water, etching solutions and alcohols, or gases such as air, nitrogengas and argon gas, or a [liquid and gas] mixture wherein a liquid and agas are mixed at an appropriate ratio, besides using a water jet and airjet. In particular, in the case of a so-called water/air jet which is aninjection of a jet consisting of a liquid and a gas, gas bubbles arepresent in the liquid so that separation can be carried out effectivelyusing an impact action when the bubbles are ruptured.

If ultrasonic waves are applied to the fluid when a high pressure fluidjet 82 is blown, vibration of ultrasonic waves acts on the porous layerand separation from the porous layer can be carried out moreeffectively. Furthermore, powders or ultra fine powders (polishingagents, ice, plastic chips, etc.) can be added as micro solids to thehigh pressure fluid jet 82. If such a micro solid is added, separationcan be carried out more effectively because the micro solid directlycollides with the high porous Si layer 11 b.

If an ultra fine powder of granules and powders is added to the highpressure fluid jet 82 and ultrasonic waves are also applied at the sametime, more efficient separation can be achieved.

Laser process stripping equipment (not shown) can be used in order toseparate a separation layer from the rotating substrate by applyinglaser lights emitted from the laser output unit. A difference in thelaser process stripping equipment from said high pressure fluid jetstripping equipment is only the fact that the laser output unit isequivalent to a combination of said micro nozzle 83 with a slit hole 84and the rest of the structure is almost identical.

In the laser process stripping equipment, it is possible to separate thehigh porous Si layer 11 b by laser processes (abrasion processes,thermal processes, etc.) by irradiation of more than one laser from thehorizontal plane of the high porous Si layer 11 b of the rotatingsubstrate.

Lasers including visible light, near UV-rays, far UV-rays, near infraredrays and far infrared rays, such as carbon dioxide gas lasers, YAG(Yttrium Aluminum Garnet) lasers, excimer lasers and harmonic modulationlasers are available.

Laser processes can be divided into two categories: a method ofseparation by thermal processes or ablation processes by irradiation ofat least one or more pulsed or continuous wave laser lights that atarget subject can absorb; and another method of separation in which atleast one or more pulsed or continuous wave near infrared lasers (Nd:YAG lasers, Nd: YVO4 lasers, Nd: YLF lasers, titanium and sapphirelasers, etc.) having a wavelength transmitting through a target subjectare emitted to be focused in the inside of the target subject and aphenomenon of optical damaging is generated by multiphoton absorption tocreate a reformed region (e.g., cracked region, fusion treated region,regions with altered refractive index, etc.) wherein separation occursusing a relatively small force.

In general, in the latter case, if a processing target is irradiated bylaser lights under conditions with a peak power density of 1×10⁸ (W/cm²)or greater (electrical field intensity at the focal point of the pulsedlasers) and a pulse width of 1 μS or less while focusing at the interiorof the processing target which is, the interior of a monocrystallinesemiconductor substrate, optical damage is caused by multiphotonabsorption in the interior of the processing target and thermaldistortion is induced due to such optical damage. As a result, areformed region, for example, a cracked region, is formed in theinterior wherein separation occurs using a relatively small force. Whencompared to a monocrystalline semiconductor layer, in the cases of aporous semiconductor layer of this invention and a monocrystallinesemiconductor layer of the ion injected layer as will be mentioneddiscussed later, it is possible to form a reformed region when aphenomenon of optical damaging occurs due to multiphoton absorptionbelow the aforesaid peak power density (e.g., cracked region, fusiontreated region, regions with an altered refractive index, etc.) andthus, separation from a porous semiconductor layer and an ion injectedlayer as will be mentioned later can be carried out easily by laserprocesses.

In the case of laser processes, laser lights is converged through acollective lens at the interior of the processing target (namely theinterior of the porous semiconductor layer and ion injected layer aswill be discussed later) and the target can be separated by graduallymoving the focal point into the interior of the processing target. Inparticular, in the case of the present invention, a porous Si layer oran ion injected layer is a processing target so that the separationprocess using laser lights can be performed highly efficiently. Ifdesirable, a Si substrate 10 can be separated from a porous Si layerwhile cooling the side of the facing substrate 21 via a UV tape using asupport device which is cooled with a fluid.

Laser water jet process stripping equipment (not shown) can be used inorder to separate a high porous Si layer 11 b from the rotatingsubstrate by irradiation of a laser water jet in combination with laserlights and a water jet from the output unit. A difference in the laserwater jet process stripping equipment from said laser process strippingequipment and said high pressure fluid jet stripping equipment is onlythe fact that the laser water output unit is equivalent to a combinationof said micro nozzle 83 with a slit hole 84 and the rest of thestructure is almost identical.

The method of laser water jet process stripping uses the advantages ofboth water jet and lasers. Based on the fact that laser lights arisecompletely reflected on the boundary between water and air, all laserlights is are totally reflected by the water jet as in glass fibers andguided in the parallel direction and separation occurs due to thermalprocesses and ablation processes caused by absorption of laser lights.Unlike the conventional laser processes in which thermal deformation isthe subject of concern, [the equipment] is always cooled with water inthe case of a laser water jet so that the thermal effects on theseparating surface, for example, thermal deformations, can be reduced.

According to the laser water jet process exfoliation method, one or morelaser water jets in which at least one or more pulsed or continuous nearinfrared lasers (Nd: YAG lasers, Nd: YVO₄ lasers, Nd: YLF lasers,titanium and sapphire lasers, etc.) are sealed in the water columns ofpure water or ultra pure water under an arbitrary water pressure areinjected in the horizontal direction of the porous Si layer 11 b in therotating substrate in order to apply processes (ablation processes,thermal processes, etc.) for separation from the porous Si layer 11 b.

Lasers including visible light, near UV-rays, far UV-rays, near infraredrays and far infrared rays, such as carbon dioxide gas lasers, YAG(Yttrium Aluminum Garnet) lasers, excimer lasers and harmonic modulationlasers are available. In addition, water columns for the water jetsunder an arbitrary water pressure can be provided from tap water.However, for certain types of lasers, it is desirable to use pure wateror ultra pure water as water columns for water jets wherein lasers arenot attenuated due to the absence of scattering by irregular reflection.

The aforesaid high pressure fluid jet injection exfoliation method,laser process exfoliation method and laser water jet process exfoliationmethod can also be used for manufacturing semiconductor devices such aspicture signal processing, memory LSI, CPULSI, DSPLSI, voice signalprocessing LSI, CCD, CMOS sensors and BiCMOS by separating an ultra slimsemiconductor layer or ultra slim SOI semiconductor layer.

The aforesaid high pressure fluid jet injection exfoliation method,laser process exfoliation method and laser water jet process exfoliationmethod can also be used for cutting monocrystalline or polycrystallinesemiconductor substrates or transparent or opaque support substrates,and also for slicing rotating monocrystalline or polycrystallinesemiconductor ingots.

As mentioned previously, if a groove 62 is formed from themonocrystalline Si layer 12 b at least until the high porous Si layer 11b along the division line, that is the division boundary within thescribe line, so when [the layer] is divided into single panels ofvarious ultra slim electrooptic displays, the ultra slim TFT substratelayer to be separated from the monocrystalline Si substrate 10 as asupport substrate has already been divided so that separation becomesmuch easier.

(10) The low porous Si layer 11 c and monocrystalline Si layer 12 a onthe separated surface are etched to expose a transparent resin 16 viatransparent insulating layers such as SiO₂ layer 13 a and SiO₂ layer 13b (FIG. 8 (a) shows an overview of the board, and FIG. 8(b) shows adisplay area).

The low porous Si layer 11 c and the monocrystalline Si layer 12 a aretreated by wet etching with a mixed solution of HF+H₂O₂+H₂O or a mixedsolution of HF+HNO₃+CH₃COOH, or by dry etching (plasma etching usingSF₆, CF₄, Cl⁺ O₂, HBr+O₂, reverse sputter etching, etc.). The lightoptically transparent material embedded in the pixel opening section canbe protected by transparent insulating films such as SiO₂ layer 13 a andSiO₂ layer 13 b during the etching process for the low porous Si layer11 c and the monocrystalline Si layer 12 a. Therefore, interference withquality such as light transmittance can be prevented. In the case of wetetching with a fluoric acid etching solution, it is desirable to usetransparent insulating films containing highly acid resistant siliconnitride films instead of a SiO₂ layer, for example, laminated films ofsilicon oxide and silicon nitride obtained by thermal oxidation ofsilicon nitride film, laminated films of silicon oxide, silicon nitrideand silicon oxide obtained by thermal oxidation of the laminated filmsof silicon oxide and silicon nitride, or silicon oxy-nitride films.

(11) A transparent support substrate 24 as a support is bonded on theexposed surface of the transparent resin 16 via the transparentinsulating films such as SiO₂ layer 13 a and SiO₂ layer 13 b, using aheat resistant and light resistant transparent sealant 25 a of thesilicone series, urethane series, epoxy series or acrylic series (FIG. 9(a) shows an overview of the board, and FIG. 9 (b) shows a displayarea).

In the case of transmissive type LCDs for projectors, a light resistanttransparent sealant is desirable.

In addition, it is desirable that the transparent sealant 25 a does notcontain any elements which interfere with the characteristics, such ashalogen atoms.

A low reflective and light-shielding film 26 a and a reflective film 26b are preferably formed at the portion corresponding to the poly-Si TFTsection 15 a in the display area of the transparent support substrate 24and at the portion corresponding to the poly-Si TFT section 15 a in thedisplay area of the facing substrate 21, respectively. In addition, itis also desirable to form a low reflective and light-shielding film 26 aand a reflective film 26 b at the respective portions corresponding toperipheral circuit areas of the transparent support substrate 24 and thefacing substrate 21.

As a result, the reflective film 26 b reflects undesirable incidentlight to increase contrast and it reduces the elevation of the liquidcrystal temperature, resulting in longer life of the panel. Furthermore,the low reflective and light shielding film 26 b reduces the TFT currentleakage due to the reflected light from the back side to increase lightresistance, in an attempt to increase luminance.

As transparent support substrates, the following materials satisfyingoptical characteristics with a linear transmittance of 80% or greaterwithout an antireflective film can be used: quartz glass, transparentcrystallized glass (Neoceram, CLEARCERAM, and Zerodur, etc.),borosilicate glass, aluminosilicate glass, microsheet glass, andtransparent plastics.

If an ultra slim electrooptic display device substrate as separatedabove is bonded using a light resistant transparent sealant to atransparent support substrate such as transparent substrates includinghigh thermal conductive glass with 10(W/m·K) satisfying opticalcharacteristics indicated by a linear transmittance of 80% or higherwithout an antireflective film; high transmissive ceramic polycrystals{electrically fused or sintered oxide crystals such as MgO (magnesia),Y₂O₃ (yttrium), CaO (calcia), Al₂O₃ (monocrystalline sapphire), BeO(beryllia), polycrystalline sapphire, or monocrystalline orpolycrystalline YAG of polyoxide crystals, monocrystalline orpolycrystalline spinels, and 3Al₂O₃.2SiO₂, Al₂O₃.SiO₂}, fluoridemonocrystals (calcium fluoride, magnesium fluoride, barium fluoride,etc.), high transmissive ceramic polycrystals or fluoride monocrystalsor transparent crystallized glass coated with a diamond film synthesizedby vapor phase reaction, and crystals; a high thermal dissipation effectagainst strong incident light is achieved, resulted in high luminance,high resolution and longer life. As a result, transmissive LCDs forprojectors can be implemented with high quality and reliability.

If said high thermal conductive glass is used as a facing substrate(micro lens substrate, black mask substrate, etc.), a dust-proof glassforms an antireflective film at the input side, and a dust-proof glassforms an antireflective film at the output side. For example, astructure from the input side comprising of monocrystalline sapphiredust-proof glass forming an antireflective film, monocrystallinesapphire facing substrate (including micro lens substrate, black masksubstrate, etc.), liquid crystal layer, ultra slim electrooptic displaydevice substrate, monocrystalline sapphire support substrate, and amonocrystalline sapphire dust-proof glass forming an anti-reflectivefilm are bonded to each other using a light resistant transparentsealant to achieve a high heat dissipation effect.

(12) The facing substrate 21, electrooptic display device substratelayer (monocrystalline Si layer 12) and transparent support substrate 24are cut along the division boundary within the scribe line. According tothe materials of the facing substrate 21 and the transparent supportsubstance 24, an appropriate cutting method can be selected: bladedicing, laser cutting processes (thermal processes and ablationprocesses such as carbon dioxide gas lasers, YAG lasers, and excimerlasers; and multiphoton absorption reforming laser processes such as Nd:YAG lasers, Nd: YVO4 lasers, Nd: YLF lasers and titanium/sapphirelasers), diamond cutter, cemented carbide cutter, ultrasonic cutter,high pressure fluid jet injection cutting processes, laser water jetcutting processes.

Subsequently, a liquid crystal 70 selected based on the method ofapplying the electrical field and alignment films is injected from theinjection hole: e.g., nematic liquid crystals (TN mode liquid crystals,VA (vertically aligned) mode liquid crystals, smetic liquid crystals(strongly electroconductive liquid crystals, non-stronglyelectroconductive liquid crystals), polymer dispersible type liquidcrystals, or other liquid crystals. If desirable, a liquid crystalalignment treatment is applied by a heating/quenching treatment toobtain transmissive LCDs.

(FIG. 10 (a) shows a transmissive LCD without a light-shielding film andFIG. 10 (b) shows a transmissive LCD with a reflective film and a lightshielding film).

The following combinations are desirable for the relationships among thealignment film, alignment treatment and liquid crystal.

In the case of an organic alignment film such as polyimide and polyamidewith a thickness of 5˜50 nm, a positive dielectric anisotropic TN modeliquid crystal is used with a rubbing process.

In the case of an organic alignment film containing a vertical alignmentagent such as polyamide with a thickness of 5˜50 nm, a negativedielectric anisotropic TN mode liquid crystal (VA mode liquid crystal)is used without a rubbing process.

In the case of an organic alignment film such as polyimide and polyamidewith a thickness of 5˜50 nm, a positive dielectric anisotropic TN modeliquid crystal is used with an ion beam irradiation process by applyingan argon ion beam with an angle of 15 to 20° against the substrate underan acceleration voltage ranging from 300 to 400 eV.

In the case of an organic alignment film such as polyimide and polyvinylcinnamate with a thickness of 5˜50 nm, a positive dielectric anisotropicTN mode liquid crystal is used with an optical alignment process byvertical irradiation of UV-rays linearly polarized at 257 nm against thesubstrate.

In the case of an organic alignment film such as polyimide and polyvinylcinnamate with a thickness of 5˜50 nm, a positive dielectric anisotropicTN mode liquid crystal is used with a laser alignment process byirradiation of a 266 nm YAG laser with an arbitrary angle of 45° againstthe substrate.

In the case of a silane alignment film in which an alkyl group forming acomplex of a silicon atom and an oxygen atom is bound to a silicon atom,a negative dielectric anisotropic TN mode liquid crystal (VA mode liquidcrystal) is used without an alignment process.

In the case of an aminosilane alignment film, a positive dielectricanisotropic TN mode liquid crystal is used with a rubbing process.

In the case of an inorganic alignment film of an oblique deposition filmof SiOx with a thickness of 10˜30 nm, a positive dielectric anisotropicTN mode liquid crystal is used with an alignment process by adjustmentof the angle of vapor deposition from the vertical direction of thesubstrate.

In the case of an inorganic alignment film of SiOx with a thickness of10˜30 nm prepared by vapor deposition of sputtering, a positivedielectric anisotropic TN mode liquid crystal is used with an ion beamirradiation process by applying an argon ion beam with an angle of 15 to20° against the substrate under acceleration voltage ranging from 300 to400 eV.

In the case of an inorganic alignment film of SiOx with a thickness of10˜30 nm prepared by mirror tron sputtering (oriented sputtering), apositive dielectric anisotropic TN mode liquid crystal is used with analignment process by adjusting a sputtering angle against the substrate.

In the case of an inorganic alignment film of DLC (diamond like carbon)with a thickness of 5˜20 nm prepared by CVD, a positive dielectricanisotropic TN mode liquid crystal is used with an ion beam irradiationprocess by applying an argon ion beam with an angle of 45° against thesubstrate under acceleration voltage ranging from 300 to 400 eV.

A PETF (approximately 50 nm: polytetrafluoroethylene) film is formed asa second alignment film by ion vapor deposition on the first alignmentfilm processed by aforesaid processes 1˜11 and a positive dielectricanisotropic TN mode liquid crystal is used.

A PE (approximately 50 nm: polyethylene) film is formed as a secondalignment film by ion vapor deposition on the first alignment filmprocessed by aforesaid processes 1˜11 and a positive dielectricanisotropic TN mode liquid crystal is used.

A biphenyl-4,4′-dimethacrylate (approximately 50 nm: polyethylene) filmis polymerized as a second alignment film by ion vapor deposition on thefirst alignment film processed by aforesaid processes 1˜11 and apositive dielectric anisotropic TN mode liquid crystal is used.

In the case of an organic alignment film of polyimide and polyamide, aferroelectric (FLC) liquid crystal is used with a rubbing alignmentprocess or an optical alignment by 257 nm directly polarized UVirradiation or an ion beam alignment by argon ion beam irradiation or alaser alignment process by 266 nm YAG laser irradiation.

In the case of an organic alignment film of polyimide and polyamide, anelectrically controlled birefringence (ECB) liquid crystal is used witha rubbing alignment process or an optical alignment by 257 nm directlypolarized UV irradiation or an ion beam alignment by argon ion beamirradiation or a laser alignment process by 266 nm YAG laserirradiation.

Alternatively, before separating the Si substrate 10, the poly-Si layer14 in the portion corresponding to the pixel opening section of thedisplay section of the ultra slim TFT substrate layer is removed byetching. If desirable, a light-shielding metallic film is formed via atransparent insulating film on the poly-Si TFT section and on theinterior wall of the pixel opening section; a transparent resin 16 isembedded for surface flattening as a light optically transparentmaterial within the pixel opening section where this light shieldingmetallic film has been removed; a transparent electrode 18 a connectedto the drain of the display poly-Si TFT 15 a is formed on the top; asealant and a common agent (not shown) are coated on a non-defectivechip in the ultra slim TFT substrate obtained after an alignment processby forming an alignment film 20 a; and a non-defective chip of thefacing substrate 21 after an alignment process by forming a transparentelectrode 18 b and an alignment film 20 b is laid and sealed with aliquid crystal gap of 2 μm. Subsequently, the facing substrate 21 andthe Si substrate 10 are covered with an antistatic UV tape 23 with noresidual sealant; the Si substrate 10 is separated from the high porousSi layer 11 b for the transparent resin 16 to be exposed as a lightoptically transparent material; if desirable, the residue afterseparation is removed by etching; and a transparent support substrate 24is bonded using a transparent sealant.

In this execution form, an ultra slim electrooptic display devicesubstrate layer (monocrystalline Si layer 12) is obtained by separating[the bottom portion] so that an ultra slim electrooptic display devicesubstrate is obtained with high electron and positive hole mobility in avery thin monocrystalline Si film with a thickness of 10 μm. Forexample, if a facing substrate and a transparent support substraterespectively with a thickness of approximately 100 μm are laminated, atransmissive type LCD (LCOS) with a high luminance, high resolution andhigh functionality in an ultra slim type with a thickness of about 200μm can be manufactured inexpensively with a high yield and highproductivity.

(A-2) Ultra Slim Reflective Type LCD

When manufacturing ultra slim reflective type LCDs, the processes(1)˜(4) (FIG. 1˜FIG. 3) shown in (A-1) are the same. Subsequently, asshown in FIG. 11 (a) and 11 (b), after a wiring layer 27 is formed and aprotective film 28 is formed in the peripheral circuit area, areflective electrode 19 a with a high reflective index which is made ofaluminum, aluminum-silicon alloy, silver, silver alloy, nickel, nickelalloy, titanium or titanium alloy, which is connected to the drain ofthe poly-Si TFT section 15 a for pixel display in the display area, isformed in the pixel display section.

As in aforesaid (A-1), an organic liquid crystal alignment film materialof polyimide and polyamide is formed at least for each panel, a liquidcrystal alignment process such as buff rubbing is carried out, ifdesirable, and organic cleaning with IPA (isopropyl alcohol) isperformed to form an organic liquid crystal alignment film (hereafterreferred to as an alignment film). Alternatively, an alignment film 20 acan be an inorganic alignment film which is formed as an oblique vapordeposition of SiOx.

By forming a part of peripheral circuits including memory circuits inaddition to the display circuits in the monocrystalline semiconductorlayer under a reflective electrode in the pixel display device unit inthese ultra slim reflective LCDs, an ultra slim electrooptic displaywith increased degrees of integration can be implemented inexpensivelywith high resolution, high functionality, and high quality.

Also, by forming peripheral circuits or a display device unit andperipheral circuits having a multilayer wiring structure in themonocrystalline semiconductor layer, an ultra slim electrooptic displaywith increased degrees of integration can be implemented inexpensivelywith high resolution, high functionality, and high quality.

Furthermore, by forming peripheral circuits even in the monocrystallinesemiconductor layer in the sealed region, the number of units requiredper wafer increases due to reduced TFT substrate sizes, resulting inreduced cost of production.

As described in (A-1), a sealant and a common agent (not shown) arecoated on the surface; a facing substrate 21, after a liquid crystalalignment process by buff rubbing by forming an organic liquid crystalalignment film 20 b of polyimide or polyamide by forming a transparentelectrode 18 b, is laminated and sealed with a liquid crystal gap of 2μm (See FIG. 12). In the reflective electrode 19 a, an appropriateconcave/convex shape is formed on the electrode in order to improve easein seeing the display by providing appropriate light scattering effectin the case of direct-viewing reflective LCDs.

For example, a photosensitive resin film in an appropriateconcave/convex shape is formed by common lithographic technology in thepixel display device unit and reflowed by heating; and an aluminum filmwith a high reflective index, connected to the drain of the displaypoly-Si TFT section 15 a in order to form a reflective electrode 64 inan appropriate concave/convex shape. In the cases of reflective LCDs forprojectors, it is desirable to have a very flat pixel electrode shape.

Subsequently, a Si substrate 10 and a facing substrate 21 are coveredwith a UV tape 23, and then the Si substrate 10 is separated from thehigh porous Si layer (FIG. 12).

This separation method is the same as described in (A-1). After theseparation, a metallic support substrate 29 as an opaque support isbonded using a high thermally conductive and electrically conductivesealant 25 b (FIG. 13).

In this execution form, a metal is used as a support, but resin filmsand glasses can also be used as other backing. In this case, resins andglass materials having high thermal conductivity are desirable. If thesupport is a resin film or a glass, a low-temperature curable type or UVhardening type sealant below the liquid crystal transition temperature,for example at 80° C., is used for bonding. In the case of projectors, ametal with good heat dissipation is selected as a support. In this case,for accelerating cooling and grounding to earth, it is desirable to usea low-temperature curable type sealant below the liquid crystaltransition temperature, for example at 80° C., for bonding, which ishighly heat conductive and electrically conductive due to the presenceof metallic filler.

The subsequent processes are the same as those in aforesaid (A-1).

Because a low porous Si layer 11 c remains on the bonded surface withthe metallic support substrate 29 in the ultra slim electrooptic displaydevice substrate layer (monocrystalline Si layer 12), sealing with asealant 17 is improved and it is held firmly on the metallic supportsubstrate 29. Subsequently, a liquid crystal 70, selected based on themethod of electrical application and the alignment film, for example,nematic liquid crystals (TN liquid crystals, vertically oriented liquidcrystals, etc.), smetic liquid crystals (ferroelectric liquid crystals,non-ferroelectric liquid crystals, etc.) or other liquid crystals, isinjected from the liquid crystalline injection hole for sealing. Ifdesirable, a liquid crystal alignment process is performed by applying aheating or quenching process to obtain a reflective type LCD (LCOS) asshown in FIG. 13.

In this execution form, an ultra slim electrooptic display devicesubstrate layer (monocrystalline Si layer 12) is obtained by separating[the bottom portion] so that an ultra slim electrooptic display devicesubstrate is obtained with high electron and positive hole mobility in avery thin monocrystalline Si film with a thickness of 10 μm. Forexample, if a facing substrate and a transparent support substraterespectively with a thickness of approximately 100 μm are laminated, atransmissive type LCD (LCOS) with a high luminance, high resolution andhigh functionality in an ultra slim type with a thickness of about 200μm can be manufactured inexpensively with a high yield and highproductivity.

(A-3) Ultra Slim Semi-Transmissive Type LCD

When manufacturing ultra slim semi-transmissive type LCDs, the processes(1)˜(6) (FIG. 1˜FIG. 5) shown) shown in (A-1) are the same.

Subsequently, a window is opened in the transparent resin 16 on thepoly-Si TFT section 15 a in the display area, and a TFT substrate layeris formed by forming a pixel electrode forming two regions consisting ofa reflective region and a transmissive region (FIG. 14).

In the case of semi-transmissive type LCDs, a part of the reflectiveelectrode is patterned to form a transparent electrode in order to havetwo regions consisting of a reflective region and a transmissive regionin one pixel.

For example, as shown in FIG. 14 (a), a transparent electrode 18 a ofITO or IZO, connected to the drain of the display polyl-Si TFT section15 a, is formed in the pixel opening section; a photosensitive resinfilm 63 in an appropriate concave/convex shape is formed in a part ofthe transparent electrode by a common lithographic technology; after thereflow with heating, a reflective electrode 64 in an appropriateconcave/convex shape is formed by forming an aluminum film with a highreflectance, which is connected to the transparent electrode, in orderto form a pixel electrode to form two regions consisting of a reflectiveregion and a transmissive region in one pixel.

As shown in FIG. 14 (b), a photosensitive resin film 63 in anappropriate concave/convex shape is formed in a part of the pixelopening section by a common lithographic technology; after the reflowwith heating, a reflective electrode 64 in an appropriate concave/convexshape is formed by forming an aluminum film with a high reflectance,which is connected to the drain of the display poly-Si TFT section 15 a,in order to form a pixel electrode to form two regions consisting of areflective region and a transmissive region in one pixel by forming atransparent electrode 18 a in the pixel opening section containing thealuminum film.

The balance of optical characteristics between transmission andreflection can be maintained by controlling the pixel area ratio betweentransmission and reflection.

As in the case of transmissive type LCDs, backlight sources are used fortransmissive displays in the semi-transmissive LCDs and solar lights areused for reflective displays as in the case of reflective type LCDs.

In order to achieve brighter displays using semi-transmissive type LCDs,the reflective electrode is covered even in the opaque region for wiringand TFTs to increase the opening ratio, and a transparent electrode isarranged on the area where there is no opaque wiring in an attempt toincrease the overall opening ratio.

In order to implement a paper-white look on the reflective type LCDs andsemi-transmissive type LCDs, it is necessary to optimize thedistribution shape of the angle by limiting the angle of inclination ofthe roughness formed on the reflective electrode to a specific range asa function of causing diffusion scattering by reducing the normalreflective component of the reflected light.

If the roughness is oriented regularly, optical interference of rainbowcolors occurs in the reflected images under solar light and the visualrecognition is reduced. Therefore, the roughness configuration must berandomized by applying the arrays expressed by the Fibonacci Series to aroughness pattern.

The subsequent processes are carried out as described in (A-1). On anultra slim TFT substrate layer after forming an alignment film and analignment process, a facing substrate after forming an alignment filmand an alignment process by forming a transparent electrode is laminatedand sealed with a specified liquid crystal gap of 2 μm.

Both a Si substrate 10 and a facing substrate 21 are covered at leastwith an antistatic UV tape 23 containing no residual sealant and as inthe processes in (A-1); the Si substrate is separated from the highporous Si layer 11 b in order to expose the optically transparentmaterial via a transparent insulating film at least in the pixel openingsection in the display device unit; a transparent support is bondedusing a transparent sealant on an ultra slim TFT substrate after beingseparated; and a liquid crystal is injected after the division tovarious ultra slim electrooptic displays.

The combinations in accordance with the transmissive type LCDs describedin (A-1) are applicable to the relationships among the alignment film,alignment process and liquid crystal.

A semi-transmissive LCD is produced by the following processes. Thepixel opening section in the display device unit of an ultra slimelectrooptic display device substrate layer (monocrystalline Si layer12) is etched and mounted with a optically transparent material forsurface flattening; an alignment process is carried out by forming apixel electrode having two regions consisting of a reflective region anda transmissive region, which is connected to the drain of the pixeldisplay devices and by forming an alignment film; a sealant and a commonelectrode agent are coated; a facing substrate prepared after thealignment process by forming a transparent electrode and an alignmentfilm is laminated and sealed with a specific liquid crystal gap;subsequently, the monocrystalline substrate 10 is separated; ifdesirable, the high porous Si layer and the low porous Si layer stillremaining on the optically transparent material in the exposed pixelopening section are removed by etching to expose at least the opticallytransparent material in the pixel opening section in the display deviceunit via a transparent insulating film; a transparent support substrateis bonded using a transparent sealant; a liquid crystal is injectedafter being divided into various electrooptic displays; and ifdesirable, a liquid crystal alignment process is carried out byperforming a heating and quenching process to obtain a semi-transmissivetype LCD.

The structures of an organic EL and its manufacturing methods will beexplained below.

Organic EL layers can be classified under a single layer type, a doublelayer type, and a triple layer type. The structure of the triple layertype of low molecular compounds is comprised of an anode, hole transportlayer, emission layer, electron transport layer and a cathode; or ananode, a hole transporting emission layer, carrier block layer, anelectron transporting emission layer and a cathode.

A structure of the display device unit of the TFT substrate of the uppersurface luminous type organic EL is comprised of organic EL emissionlayers of red, blue and green for each pixel, adhered on an anode(metallic electrode) such as Li—Al or Mg/Ag which are connected todrains of TFTs for driving current for each pixel; an anode (transparentelectrode) of a ITO film is formed on the top (if desirable, an anode isformed on the entire surface); and the entire surface is covered with amoisture-proof transparent resin.

In the case of an upper surface luminous type organic EL, a cathode ofLi—Al or Mg—Ag, connected to the drain of the display TFT, is formed inthe pixel display device unit. If the cathode covers the MOSTFT MOSTFETfor driving current increases its emission area so that the cathodebecomes a light shielding film. Therefore, its auto-emission light doesnot enter the MOSTFETMOSTFT. For this reason, there is no generation ofleak current and the interference with TFT characteristics can beavoided.

In the display device unit of the TFT substrate in the lower surfaceluminous type organic EL, organic EL emission layers are coated for eachpixel such as red, blue and yellow on an anode (transparent electrode)of a ITO film, connected to the sources of the TFT for driving thecurrent for each pixel, a cathode (metallic electrode) of Li—Al or Mg—Agis formed on the top (if desirable, a cathode is formed on the entiresurface), and the entire surface is covered with a moisture-proof resin.This sealing prevents external invasion of moisture, deterioration ofthe organic EL emission layer which is sensitive to moisture andelectrolytic oxidation are prevented, making long life, high quality andhigh reliability possible.

(A-4) Ultra Slim Lower Surface Luminous Type Organic EL:

In the case of ultra slim lower surface luminous type organic ELs, theprocesses are almost the same as those of ultra slim transmissive typeLCDs as described in (A-1). Before separating the Si substrate 10, theportion corresponding to the pixel opening section in the display areaof the ultra slim TFT substrate is removed by etching; if desirable,after forming a transparent insulating film and a light shieldingmetallic film within the pixel opening section, the light-shieldingmetallic film at the bottom of the pixel opening is removed and thepixel opening is embedded with a transparent resin (not shown) as alight optically transparent material for surface flattening; an anode ofan ITO film (transparent electrode 60 c), connected to the source of thepoly-Si TFT section 15 a for driving the current) for each pixels in thepoly-Si layer 14 in the display area, is formed on the planarized film;furthermore, an organic EL emission layer 60 b of red, blue and greenfor each pixel, is coated and a cathode of Li—Al or Mg—Ag (metallicelectrode 60 a) is formed on the top (if desirable, a cathode is formedon the entire surface); and the entire surface is covered with amoisture-proof transparent resin 61.

Subsequently, the moisture-proof transparent resin 61 and the Sisubstrate 10 are covered with at least an antistatic UV tape 23 withoutresidual sealant; the Si substrate 10 is then separated from the highporous Si layer 11 b; the low porous Si layer 11 c and themonocrystalline Si layer 12 a on the surface separated are etched inorder to expose the transparent resin embedded in the pixel openingsection in the display area via the transparent insulating layers suchas SiO2 layer 13 a and SiO2 layer 13 b; and a transparent supportsubstrate 24 is bonded using a transparent sealant 25 a (FIG. 15).

The sealing with the moisture-proof transparent resin 61 preventsexternal invasion of moisture and also prevents deterioration of theorganic EL emission layer which is sensitive to moisture andelectrolytic oxidation, making long life, high quality and highreliability possible. In this case, it is desirable that the height ofthe external output electrode 66 containing bumps is lower than theheight of the moisture-proof transparent resin 61.

(A-5) Ultra Slim Upper Surface Luminous Type Organic EL:

In the case of ultra slim upper surface luminous type organic ELs, theprocesses are almost the same as those of ultra slim reflective typeLCDs as described in (A-2);

an organic EL emission layer 60 b of red, blue and green for each pixel,is coated on the cathode of Li—Al or Mg—Ag (metallic electrode 60 a),connected to the drain of the poly-Si TFT section 15 a for driving thecurrent for each pixels in the poly-Si layer 14 in the display area andan anode of ITO film (transparent electrode 60 c) is formed on the top(if desirable, a cathode is formed on the entire surface); and theentire surface is covered with a moisture-proof transparent resin 61 asin the case of ultra slim lower surface luminous type organic ELs.

Subsequently, the moisture-proof transparent resin 61 and the Sisubstrate 10 are covered with at least an antistatic UV tape 23 withoutresidual sealant; the Si substrate 10 is then separated from the highporous Si layer 11 b; and a metallic support substrate 29 is bondedusing a high thermally conductive and electrically conductive sealant(See FIG. 16).

The sealing with the moisture-proof transparent resin 61 preventsexternal invasion of moisture and also prevents deterioration of theorganic EL emission layer which is sensitive to moisture andelectrolytic oxidation, making long life, high quality and highreliability possible.

If a part of the peripheral circuits including memory circuits is alsoformed in addition to the display circuits in the monocrystallinesemiconductor layer under the reflective electrode in the pixel displaydevice unit in the case of ultra slim upper surface luminous typeorganic ELs, the degree of integration is improved and ultra slimelectrooptic displays can be implemented inexpensively with highresolution, high functionality and high quality.

Furthermore, it is desirable that the height of the external outputelectrode 66 containing bumps is lower than the height of themoisture-proof transparent resin 61.

In this execution form, the monocrystalline Si layer 12 a of the Sisubstrate 10 is thermally oxidized to form a SiO₂ layer 13 a; the SiO₂layer 13 a in the peripheral circuit area is removed while leaving theSiO₂ layer 13 a in the display area; a poly-Si layer 14 in the displayarea and a monocrystalline Si layer 12 b in the peripheral circuit areaare formed, respectively by means of semiconductor epitaxial growth suchas CVD in order to form a poly-Si TFT section 15 a as a display deviceunit in the poly-Si layer 14 in the display area and a monocrystallineSi TFT section 15 b as a peripheral circuit unit in the monocrystallineSi layer 12 b in the peripheral circuit area. As a result, poly-Si TFTdisplay devices with a relatively low electron and positive holemobility with low current leakage qualities and monocrystalline Si TFTperipheral circuits with a high electron and positive hole mobility witha high drivability can be formed within an ultra slim TFT substratelayer on the same Si substrate 10. Therefore, an ultra slim electroopticdisplay with a high electron and positive hole mobility and low currentleakage qualities can be produced with high luminance, high resolution,and high functionality.

In this case, an amorphous Si layer is formed selectively by ionimplantation of elements of Group IV, for example, highly concentratedSi ions on the surface of the poly-Si layer in the display area; and apoly-Si TFT section 15 a is formed as a display device unit on thesurface layer of the poly-Si layer 14 wherein the crystal grain sizes(electron and positive hole mobility) are arbitrarily controlled by thesolid phase deposition. As a result, poly-Si TFT display devices witharbitrarily controlled electron and positive hole mobility with lowcurrent leakage qualities and the monocrystalline Si TFT peripheralcircuits with a high electron and positive hole mobility with a highdrivability can be formed within an ultra slim TFT substrate layer onthe same Si substrate 10. Therefore, an ultra slim electrooptic displaywith a high electron and positive hole mobility and low current leakagequalities can be produced with high luminance, high resolution, and highfunctionality.

If at least one of the group IV elements including Ge (germanium), Sn(tin), Pb (lead), is added in an proper quantity (for example,1×10¹⁸˜1×10²⁰ atoms/cc) to the poly-Si layer 14 where in the crystalgrain sizes have been controlled by solid phase deposition, theirregularities present in the crystalline grain field of the poly-Silayer are reduced so that its film stress is also reduced. As a result,a high quality poly-Si TFT is obtained with high carrier mobility.

Alternatively, if only the poly-Si layer 14 is selectively irradiated bya flash lamp such as a xenon lamp, or by pulsed or continuous laserirradiation such as irradiation of XeCl excimer lasers, optical harmonicmodulated Nd:YAG lasers, visible light lasers, and infrared lasers, orirradiation using condensing lamps such as ultra high pressure mercurylamps, halogen lamps or xenon lamps; a poly-Si TFT section 15 a isformed as a display device unit on the surface layer of the poly-Silayer 14 where crystal grain sizes are arbitrarily controlled byre-crystallization. As a result, poly-Si TFT display devices witharbitrarily controlled electron and positive hole mobility with lowcurrent leakage qualities and the monocrystalline Si TFT peripheralcircuits with a high electron and positive hole mobility with a highdrivability can be formed within an ultra slim TFT substrate layer onthe same Si substrate 10. Therefore, an ultra slim electrooptic displaywith a high electron and positive hole mobility and low current leakagequalities can be produced with high luminance, high resolution, and highfunctionality.

In this case, if at least one of the group IV elements including Ge,tin, or lead is added in an proper quantity (for example, 1×10¹⁸ ˜1×10²⁰atoms/cc) to the poly-Si layer where the crystal grain sizes have beencontrolled by flash lamp annealing, pulsed or continuous wave laserannealing, or condensing lamp annealing, the irregularities present inthe crystalline grain field of the poly-Si layer are reduced so that itsfilm stress is also reduced. As a result, a high quality poly-Si TFTdisplay device is obtained with high carrier mobility.

In this case, a SiGe layer 12 a is formed as a distortion impressedsemiconductor layer on the Si substrate 10; a SiO₂ layer 13 a is formedby thermal oxidation; the SiO₂ layer 13 a in the peripheral circuit areais removed while leaving the SiO₂ layer 13 a in the display area; apoly-Si layer 14 is formed in the display area and a distorted Si layer12 b is formed using the a distortion impressed semiconductor layer ofSiGe layer as a seed in the peripheral circuit area, respectively bymeans of semiconductor epitaxial growth such as CVD. As a result,monocrystalline Si MOSTFT peripheral circuits with a high drivingcapacity is implemented due to significantly improved electron mobilitywhich is greater by 76-fold when compared to the monocrystalline Silayer of the conventional non-distorted channel layer.

Furthermore, an insulating layer of SiO₂ layer 13 a, and amorphous Silayer or amorphous/poly-Si mixed layer or poly-Si layer 14 is formed onthe monocrystalline Si layer 12 a by plasma CVD, thermal CVD, sputteringor vapor deposition; the SiO₂ layer 13 a and amorphous Si layer oramorphous/poly-Si mixed layer or poly-Si layer 14 in the peripheralcircuit area is removed while leaving the SiO₂ layer 13 a and amorphousSi layer or amorphous/poly-Si mixed layer or poly-Si layer 14 in thedisplay area; amorphous Si TFT or amorphous/poly-Si mixed TFT or poly-SiTFT section 15 a is formed as a display device unit in the amorphous Silayer or amorphous/poly-Si mixed layer or poly-Si layer 14 in thedisplay area; a monocrystalline Si TFT section 15 b as a peripheralcircuit unit in the monocrystalline Si layer 12 b in the peripheralcircuit area. As a result, amorphous Si TFT or amorphous/poly-Si mixedTFT or poly-Si TFT display devices with a relatively low electron andpositive hole mobility with low current leakage qualities and themonocrystalline Si TFT peripheral circuits with a high electron andpositive hole mobility with a high drivability can be formed within anultra slim TFT substrate layer on the same Si substrate 10. Therefore,an ultra slim electrooptic display with a high electron and positivehole mobility and low current leakage qualities can be produced withhigh luminance, high resolution, and high functionality.

In this case, an element of Group IV, for example, highly concentratedSn ions is selectively implanted on the surface of an amorphous Si layeror amorphous/poly-Si mixed layer or poly-Si layer 14 in the displayarea; and a poly-Si TFT section 15 a is formed as a display device uniton the surface layer of the poly-Si layer 14 wherein the crystal grainsizes (electron and positive hole mobility) are arbitrarily controlledby the solid phase deposition. As a result, poly-Si TFT display deviceswith arbitrarily controlled electron and positive hole mobility with lowcurrent leakage qualities and the monocrystalline Si TFT peripheralcircuits with a high electron and positive hole mobility with a highdrivability can be formed within an ultra slim TFT substrate layer onthe same Si substrate 10. Therefore, an ultra slim electrooptic displaywith a high electron and positive hole mobility and low current leakagequalities can be produced with high luminance, high resolution, and highfunctionality.

If at least one of the group IV elements including Ge (germanium), Sn(tin), Pb (lead), is added in an proper quantity (for example, 1×10¹⁸˜1×10²⁰ atoms/cc) to the poly-Si layer 14 where in the crystal grainsizes have been controlled by solid phase deposition, the irregularitiespresent in the crystalline grain field of the poly-Si layer are reducedso that its film stress is also reduced. As a result, a high qualitypoly-Si TFT is obtained with high carrier mobility.

Alternatively, if only the amorphous Si layer or amorphous/poly-Si mixedlayer or poly-Si layer 14 is selectively irradiated by a flash lamp suchas a xenon lamp, or by pulsed or continuous laser irradiation such asirradiation of XeCl excimer lasers, optical harmonic modulated Nd:YAGlasers, visible light lasers, and infrared lasers, or irradiation usingcondensing lamps such as ultra high pressure mercury lamps, halogenlamps or xenon lamps; a poly-Si TFT section 15 a is formed as a displaydevice unit in the poly-Si layer 14 where crystal grain sizes arearbitrarily controlled by re-crystallization. As a result, poly-Si TFTdisplay devices with arbitrarily controlled electron and positive holemobility with low current leakage qualities and the monocrystalline SiTFT peripheral circuits with a high electron and positive hole mobilitywith a high drivability can be formed within an ultra slim TFT substratelayer on the same Si substrate 10. Therefore, an ultra slim electroopticdisplay with a high electron and positive hole mobility and low currentleakage qualities can be produced with high luminance, high resolution,and high functionality.

In this case, if at least one of the group IV elements including Ge,tin, lead is added in an proper quantity (for example, 1×10¹⁸ ˜1×10²⁰atoms/cc) to the poly-Si layer wherein the crystal grain sizes have beencontrolled by re-crystallization by flash lamp annealing, pulsed orcontinuous wave laser annealing, or condensing lamp annealing, theirregularities present in the crystalline grain field of the poly-Silayer are reduced so that its film stress is also reduced. As a result,a high quality poly-Si TFT display device is obtained with high carriermobility.

(B) Method of Separation of a Double Porous Semiconductor Layer

In this execution form, a method of manufacturing an ultra slimelectrooptic display by separation of a double porous semiconductorlayer using a porous Si layer (a seed semiconductor substrate isseparated from the porous semiconductor layer formed on the seedsemiconductor substrate, and then a support semiconductor substrate isseparated from the porous semiconductor layer formed on the supportsemiconductor) will be explained below. FIG. 17 through FIG. 25 areprocess diagrams for manufacturing an ultra slim LCD by separation of adouble porous Si layer in the preferred execution form of the presentinvention.

A porous Si layer is formed by an anodic formation method respectivelyon a seed substrate 30 and a support substrate 33 (See FIG. 17). In thiscase, a high porous Si layer 31 b with a higher porosity and with agreater thickness is formed on the seed substrate 30 when compared tothe high porous Si layer 34 b on the support substrate 33.

Initially, p-type impurities are added in an approximately boron densityof 1×10¹⁹ atoms/cm³ by a CVD method using monosilane gas or diborane gasto a p-type monocrystalline Si substrate (substrate (resistivity:0.01˜0.02Ω·cm) 30 to form a high density semiconductor epitaxial growthmonocrystalline Si layer with a thickness of approximately 10 μm(corresponding to a low porous Si layer 31 a as will be mentionedlater).

On a surface of this high density layer, p-type impurities are added inan approximately boron density of 5×10¹⁴ atoms/cm³ by a CVD method usingmonosilane gas or diborane gas to form a low density semiconductorepitaxial growth monocrystalline Si layer with a thickness ofapproximately 201 μm (corresponding to a high porous Si layer 31 b aswill be mentioned later).

Furthermore, on a surface of this low density layer, p-type impuritiesare added in an approximately boron density of 5×10¹⁹ atoms/cm³ by a CVDmethod using monosilane gas or diborane gas to form a high densitysemiconductor epitaxial growth monocrystalline Si layer with a thicknessof approximately 5 μm (corresponding to a low porous Si layer 31 c aswill be mentioned later).

In the formation of a monocrystalline Si layer by a CVD method inaddition to raw materials for hydrides such as monosilane (SiH₄), thefollowing raw material gases can be used: the same raw materials forhydrides such as disilane (Si₂H₆), trisilane (Si₃H₈), and tetrasilane(Si₄H₁₀) and raw material for hydrides such as dichlorosilane (SiH₂Cl₂),trichlorisilane (SiHCl₃), and silicon tetrachloride (SiCl₄) A method offorming a monocrystalline Si layer is not limited to a CVD method, and aMBE (Molecular Beam Epitaxy) method or a sputtering method can also beapplied.

Subsequently, an anodic formation method is applied using a mixedsolution of a 50% hydrogen fluoride solution and ethyl alcohol at avolumetric ratio of 2:1 as an electrolyte, while a current is appliedfor 5 to 10 minutes at about approximately a current density of 10mA/cm² to form low porous Si layers 31 a and 31 c with a low porosity inthe high density layer and a high porous Si layer 31 b with a highporosity in the low density layer.

As mentioned above, p-type impurities are added in an approximatelyboron density of 1×10¹⁹ atoms/cm³ by a CVD method using monosilane gasor diborane gas to a p-type monocrystalline Si substrate (resistivity:0.01˜0.02Ω·cm) 33 to form a high density semiconductor epitaxial growthmonocrystalline Si layer with a thickness of approximately 10 μm(corresponding to a low porous Si layer 34 a as will be mentionedlater).

On] On a surface of this high density layer, p-type impurities are addedin an approximately boron density of 1×10¹⁵ atoms/cm³ by a CVD methodusing monosilane gas or diborane gas to form a low density semiconductorepitaxial growth monocrystalline Si layer with a thickness ofapproximately 5 μm (corresponding to a high porous Si layer 34 b as willbe mentioned later).

Furthermore, on a surface of this low density layer, p-type impuritiesare added in an approximately boron density of 3×10¹⁹ atoms/cm³ by a CVDmethod using monosilane gas or diborane gas to form a high densitysemiconductor epitaxial growth monocrystalline Si layer with a thicknessof approximately 10 μm (corresponding to a low porous Si layer 34 c aswill be mentioned later).

In the formation of a monocrystalline Si layer by a CVD method inaddition to raw materials for hydrides such as monosilane (SiH₄), thefollowing raw material gases can be used: the same raw materials forhydrides such as disilane (Si₂H₆), trisilane (Si₃H₈), and tetrasilane(Si₄H₁₀) and raw material for hydrides such as dichlorosilane (SiH₂Cl₂),trichlorisilane (SiHCl₃), and silicon tetrachloride (SiCl₄) A method offorming a monocrystalline Si layer is not limited to a CVD method, and aMBE (Molecular Beam Epitaxy) method or a sputtering method can also beapplied.

Subsequently, an anodic formation method is applied using a mixedsolution of a 50% hydrogen fluoride solution and ethyl alcohol at avolumetric ratio of 2:1 as an electrolyte, while a current is appliedfor 5 to 10 minutes at about approximately a current density of 10mA/cm² to form low porous Si layers 34 a and 34 c with a low porosity inthe high density layer and a high porous Si layer 34 b with a highporosity in the low density layer.

If a porous layer is formed by an anodic formation method, porous layersare comprised of plural numbers of layers with different porosities. Forexample, as mentioned above, a first low porous Si layer 31 a is formedon the seed substrate 30 followed by the formation of a high porous Silayer 31 b, and a second low porous Si layer 31 c in this order toachieve a triple layer structure. In addition, a double layer structurecan be obtained by forming a high porous Si layer 31 b and a low porousSi layer 31 c in this order on the seed substrate 30. As in the case ofa support substrate 33, a double layer structure can be obtained byforming a high porous Si layer 34 b and a low porous Si layer 34 c inthis order on the seed substrate 30.

In this case, the porosity ranges from 40 to 80% in the high porous Silayer, whereas the porosity in the low porous Si layer ranges from 10 to30%. The respective thickness of plural numbers of layers havingdifferent porosities can be adjusted arbitrarily by changing the currentdensity and time during the anodic formation, and kinds orconcentrations of the chemical solution during the anodic formation.

After forming a porous layer Si, it is desirable to oxidize the interiorwall of the porous Si hole with a thickness of 1 to 3 nm by dryoxidation at about 400° C. This can prevent the structural changes dueto the subsequent high temperature process for the porous Si.

For the low porous Si layers 31 c and 34 c, it is preferable that theimpurity concentrations are high (1×10¹⁰ atoms/cm3 or greater) and thatthe porosity is kept as low as possible (10˜30%). The reason for this isthat monocrystalline Si layers 32 and 35 with excellent crystallinitymust be formed on these low porous Si layers 31 c and 34 c in order toform semiconductor devices as will be discussed later.

In order to reduce distortions in the monocrystalline Si layer 32 (FIG.18) as will be discussed later, it is desirable to satisfy the followingconditions:

-   Porosity: Low porous Si layer 31 c<Low porous Si layer 34 c-   Film thickness: Low porous Si layer 31 c<Low porous Si layer 34 c

It is desirable to satisfy the following conditions in order to makeseparation of the seed substrate 30 easier in the subsequent processesand in order to prevent the separation of support substrate 33 whenseparating the seed substrate 30:

-   Porosity: High porous Si layer 31 b> High porosity Si layer 34 b-   Film thickness: High porous Si layer 31 b>High porosity Si layer 34    b

Since the anodic reaction of Si in the hydrogen fluoride solutionrequires positive holes for the dissolution reaction of Si in the anodicformation, it is desirable to use a p-type Si substrate which easilybecomes a porous substrate. However, the application is not limited tothis material.

Besides the monocrystalline Si substrate which is prepared as a Sisubstrate by the CZ (Czochralski) method, MCZ (Magnetic Field AppliedCzochralski) method, or FZ (Floating Zone) method, a monocrystalline Sisubstrate which has been treated by hydrogen annealing on its substratesurface and an epitaxial monocrystalline Si substrate can be used as aseed substrate 30 and support substrate 33.

Of course, instead of monocrystalline Si substrates, monocrystallinecompound semiconductor substrates such as monocrystalline SiGesubstrate, SiC substrates, GaAs substrates and InP substrates can beused.

(2) Monocrystalline Si layers 32 and 35 prepared by semiconductorepitaxial growth are formed respectively as monocrystallinesemiconductor layers on the seed substrate 30 or support substrate 33. ASiO₂ oxide film as an insulating film 36 or laminates of SiO₂, Si₃N₄ andSiO₂ can be formed on at least one of these monocrystalline layers (FIG.17). The important point to be considered is to make the thickness ofthe monocrystalline Si 32 thinner than that of the monocrystalline Silayer 35.

Initially] Initially, in the CVD semiconductor epitaxial growthequipment, the low porous Si layers 31 c and 34 c are pre-baked at 1000to 1100° C. under a hydrogen atmosphere to seal the surface pores tomake the surface flatter. Subsequently, the temperature is lowered to1020° C. and CVD is applied using silane gas to form monocrystalline Silayers 32 and 35.

As mentioned above, in the formation of a monocrystalline Si layer by aCVD method, a vapor phase epitaxy, in addition to hydrogenation rawmaterials such as monosilane (SiH₄), the following raw material gasescan be used: same hydrogenation raw materials such as disilane (Si₂H₆),trisilane (Si₃H₈), and tetrasilane (Si₄H₁₀) and halogenation rawmaterials such as dichlorosilane (SiH₂Cl₂), trichlorisilane (SiHCl₃),and silicon tetrachloride (SiCl₄). A method of forming a monocrystallineSi layer is not limited to a CVD method, and a MBE (Molecular BeamEpitaxy) method or a sputtering method can also be applied.

If devices are produced from the monocrystalline Si layer 32 prepared bysemiconductor epitaxial growth on the seed substrate 30, its filmthickness must be equal to or greater than that of the monocrystallineSi layer 35 prepared by epitaxial growth on the other support substrate33. The reason for this is to reduce or prevent the occurrence ofdistortions in the monocrystalline Si layer 32 prepared by semiconductorepitaxial growth.

A desirable thickness of the monocrystalline Si layer 32 prepared bysemiconductor epitaxial growth for devices ranges from 1 to 3 μm and adesirable thickness of the monocrystalline Si layer 35 would be 510 μmsince this layer is ultimately removed [before devices are prepared].

The desirable thickness for the SiO₂ oxide film (an insulating layer36), of the monocrystalline Si layer 35 ranges from 200 to 300 nm. Ifthe film becomes thicker by um unit by long-term thermal oxidation,distortions occur in the monocrystalline Si layer 35 due to the effectsof thermal oxidation of high porous Si layer 34 b.

Besides the silicon oxide film SiO₂ prepared by thermal oxidation, aninsulating film 36 can be provided as a laminated film of a siliconoxide film and a silicon nitride film, or a laminated film of a siliconoxide film, a silicon nitride film, and a silicon oxide film (e.g.,SiO₂; 200 nm, Si₃N₄; 50 nm and SiO₂; 200 nm) which is prepared byforming a silicon nitride film (Si₃N₄) or a silicon nitride film and asilicon oxide film on the monocrystalline Si layer 35 by vacuum thermalCVD followed by thermal oxidation.

Furthermore, a silicon oxy-nitride film (SiON) can be applied.

The aforementioned insulating layer of a single layer film and multiplelayer film can be formed by a plasma CVD method, sputtering method, MBEmethod and vapor deposition method.

The presence of a silicon nitride film with an appropriate filmthickness can prevent contamination of the monocrystalline Si layer 32due to penetration of halogen atoms from the side of the supportsubstrate 33 during the subsequent processes including LCD assembly andsemiconductor device processes. Also, it can reduce or prevent theoccurrence of distortions in the monocrystalline Si layer 35 formed byepitaxial growth for preparation of semiconductor devices, which arecaused by swelling by oxidation of high porous Si layer 34 b during thesemiconductor device processes. Furthermore, this silicon nitride filmfunctions as an etching stopper during the etching process for themonocrystalline Si layer 32 and low porous silicon layer 31 c so thatuneven etching can be prevented.

When etching the porous Si layer underneath the insulating layer with anultra slim SOI structure after the separation, it [the silicon nitridefilm] also acts as an etching stopper so that an ultra slim electroopticdisplay device substrate with an ultra slim SOI structure can beobtained without uneven etching.

As countermeasures against electrostatic damage and electromagneticshielding during LCD assembly or organic EL assembly, assembly of setsand for the general market, n-type or p-type impurities are added in anarbitrary concentration to the monocrystalline Si layer 35 at the timeof ion implantation or epitaxial growth and are activated during theformation of oxide films. Therefore, the addition of n-type or p-typeimpurities in an arbitrary concentration to the monocrystalline Si layer35 underneath the insulating layer 36 which remains to the last stagecan improve quality and reliability of the electrooptic displays.

(3) Bonding the Seed Substrate 30 to the Supporting Substrate (See FIG.18)

Both surfaces of the monocrystalline Si layer 332 of the seed substrate30 and the insulating layer 36 of the support substrate 33 are broughtinto contact with each other and bonded by means of Van der Waals forcesat room temperature. Subsequently, [the surfaces] are covalently bondedby a thermal processing at 400° C. for 30 minutes to strengthen thebonding. If desirable, a further thermal processing can be applied at ahigher temperature of 1000° C. for 30 to 60 minutes to furtherstrengthen the bonds.

A thermal processing can be carried out under nitrogen gas, inert gas,or mixed gas of nitrogen and inert gases. In this case, the absence ofdust and stains on surfaces of both substrates must be checked. If thereare any foreign objects, they should be cleaned.

Two sheets of substrates [wafers] are laminated in a vacuum thermalprocessing furnace where they are set under a specific reduced pressure(e.g., 133 Pa (1 Torr) or less) using a vacuum pump. After a certainperiod, substrates are exposed under atmospheric pressure so that theyare adhered tightly under pressure followed by continuous operation forthermal bonding by continuous heating under nitrogen gas or inert gases,or gas mixture of nitrogen and inert gas.

Prior to the bonding procedure, the contact surfaces can be irradiatedwith an inert gas ion beam or an inert gas high speed atomic beam forsputtering in vacuum at room temperature. Bonding forces are added onthe contact surfaces by removing dust and stains on the surface in orderto increase surface smoothness so that the bonding force can bestrengthened.

(4) Separating the Seed Substrate 30 from the High Porous Si Layer 31 b(See FIG. 19)

The separation method is based on (A).

According to high pressure fluid jet spray exfoliation method usingwater jets, air jets, or water and air jets, or laser processexfoliation method or laser/water jet process exfoliation method, theseed substrate 30 is separated from the high porous Si layer 31 b (SeeFIG. 19).

The monocrystalline Si substrate of the seed substrate 30 afterseparation is if desirable, treated by surface polishing, etching orthermal processing under atmosphere containing hydrogen and can berecycled.

Ax shown in FIG. 41 (a) and (b), it is desirable to set the diameter ofthe seed substrate 30 forming a monocrystalline semiconductor layer 32via porous semiconductor layers 31 a, 31 b and 31 c to be slightlysmaller or larger than the diameter of the support substrate 33 forminga monocrystalline semiconductor layer 35 via porous semiconductor layers34 a, 34 b, and 34 c.

A high pressure fluid jet is injected directly in the horizontaldirection in the case when the seed substrate diameter>support substratediameter as shown in FIG. 41 (a) or at an arbitrary angle from the upperdirection in the case when the seed substrate diameter<support substratediameter as shown in FIG. 41 (b) against the high porous semiconductorlayer 31 b of the seed substrate 30 to separate the seed substrate 30and at the same time, a high pressure fluid jet force towards the highporous semiconductor layer 34 b of the support substrate 33 is weakenedsuch that the support substrate is not separated from high poroussemiconductor layer 34 b of the support substrate 33.

Also, in the double porous semiconductor layer separation method, it isdesirable that the porous semiconductor layer formed on the seedsubstrate has higher porosity than the porous semiconductor layer formedon the support substrate. Furthermore, it is desirable that the poroussemiconductor layer formed on the seed substrate is thicker than theporous semiconductor layer formed on the support substrate.

In this manner, separation of the seed substrate is carried outsecurely. If the adjustment between porosity and thickness of the poroussemiconductor layers between the seed substrate 30 and the supportsubstrate 33 can be controlled, it is possible to avoid the effects ofdistortions, namely the adverse effects of thermal expansion of themonocrystalline semiconductor layer 32 on the porous semiconductorlayers 34 a, 34 b and 34 c formed on the support substrate 33 during theprocesses of forming display devices and peripheral circuits.

If C-chamfering is applied to the peripheral areas on the surface of thesupport substrate 33 including the monocrystalline semiconductor layer32 and porous semiconductor layers 31 c, 34 a, 34 b, and 34 c after theseparation of the seed substrate, it is possible to prevent chipping,cracking and breaking the ultra slim SIO layer in the peripheral areas.As a result, product yields and quality will improve and reduction ofcosts can be implemented. If desirable, a light etching process such asetching with fluoric acid etchant can be applied in order to remove Sidust and micro cracks.

(5) Residual high porous Si layer 31 and low porous Si layer 31 c areremoved by wet etching using a fluoric acid etchant or an alkalineetchant such as HF+H₂O₂+H₂O mixture, HF+HNO₃+CH₃COOH mixture.

In the case of high pressure fluid jet spray stripping which requires aphysical separation, a residual porous Si layer tends to be present sothat said wet etching is necessary. In the case of the laser processexfoliation method or laser/water jet process exfoliation method whichis separation by localized thermal fusion, the occurrence of residualporous Si layer tends to be less and wet etching is not needed and onlydry etching by a hydrogen annealing process may be sufficient.

Subsequently, monocrystalline Si layer 32 is treated by dry etching in ahydrogen annealing process to obtain a desired thickness and highflatness. For example, an ultra slim SOI structure with monocrystallineSi layer 32 with a thickness of 1 μm is formed. The hydrogen annealingprocess is carried out at an etching rate of 0.0013 nm/min at 1050° C.or at 0.0022 nm/min at 1100° C.

If desirable, a monocrystalline Si layer with a higher crystallinity andan optimal thickness can be laminated by Si epitaxial growth using themonocrystalline Si layer 32 as a seed crystal after the hydrogenannealing process.

FIG. 20 shows the status after etching. FIG. 20 (a) and (b) show a casewhen forming a SiO₂ layer 36 a as an insulating layer 36 and a case whenforming a SiO₂ layer 36 a, Si₃N₄ layer 36 b, and a SiO₂ layer 36 a as aninsulating layer 36, respectively.

(6) A SiO2 layer 13 a with a thickness of 100˜200 nm is formed bythermal oxidation of the monocrystalline Si layer, and the layer SiO₂ inthe peripheral circuit area is removed by etching while leaving the SiO₂layer 13 a in the display area. A poly-Si layer 14 with a thickness of50˜100 nm is formed in the display area and a monocrystalline Si layer12 b with a thickness of 50˜100 nm is formed in the peripheral circuitarea, respectively by the semiconductor epitaxial growth such as CVD(See FIG. 21 (a)).

All the conditions are in compliance with (A).

If desirable, the conditions when the crystal grain size of the poly-Silayer 14 (electron and positive hole mobility) in the display area arearbitrarily controlled by solid phase deposition, laser annealing, orcondensing lamp annealing are those described in (A).

In this case, the display area of the monocrystalline Si layer 32 with afilm thickness of the liquid crystal gap width or less is etched inorder to expose an insulating layer of SiO₂ layer 36 a, while leavingthe monocrystalline Si layer 32 in the peripheral circuit area.

A poly-Si layer 14 with a thickness of 50˜100 nm can be formed on theinsulating layer in the display area and a monocrystalline Si layer 12 bwith a thickness of 50˜100 nm can be formed in the monocrystalline Silayer on the peripheral circuit area, respectively by the semiconductorepitaxial growth such as CVD (See FIG. 21 (b)).

If desirable, the conditions when the crystal grain size of the poly-Silayer 14 (electron and positive hole mobility) in the display area isarbitrarily controlled by solid phase deposition or flash lampannealing, laser annealing, or condensing lamp annealing are thosedescribed in (A).

Alternatively, the conditions are those described in (A) when ifdesirable, a light shielding film 37 is formed under the TFT section ofthe poly-Si layer 14 in the display area and the crystal grain size ofthe poly-Si layer 14 (electron and positive hole mobility) in thedisplay area is arbitrarily controlled by solid phase deposition orflash lamp annealing, laser annealing, or condensing lamp annealing.

In this case, the display area of the monocrystalline Si layer 32 with afilm thickness of the liquid crystal gap width or less is etched inorder to expose an insulating layer of SiO₂ layer 36 a, and a lightshielding metallic layer 37 such as transition metal silicides includingWSi₂ (tungsten silicide), TiSi₂ (titanium silicide), MoSi₂ (molybdenumsilicide) is formed in the pixel display poly-Si TFT region in thedisplay area and subsequently covered with an insulating layer, and theinsulating layer on the monocrystalline Si layer 32 in the peripheralcircuit area is removed.

Subsequently, a poly-Si layer 14 with a thickness of 50˜100 nm can beformed on the insulating layer of SiO₂ layer 36 in the display area anda monocrystalline Si layer 12 b with a thickness of 50˜100 nm can beformed in the monocrystalline Si layer 32 on the peripheral circuitarea, respectively by the semiconductor epitaxial growth such as CVD(See FIG. 21 (c)).

If desirable, the conditions when the crystal grain size of the poly-Silayer 14 (electron and positive hole mobility) in the display area isarbitrarily controlled by solid phase deposition or flash lampannealing, laser annealing, or condensing lamp annealing are thosedescribed in (A).

In this case, a distortion impressed semiconductor layer, for example, aSiGe layer 32 with a Ge concentration of 20˜30%, is formed via theporous Si layer on the seed substrate, a SiO₂ layer 13 a is formed bythermal oxidation after bonding and separation of the seed substrate,the SiO₂ layer 13 a in the peripheral circuit area is removed whileleaving the SiO₂ layer 13 a in the display area, a poly-Si layer 14 isformed in the display area by Si epitaxial growth by CVD, and adistorted Si layer 12 b is formed as a distorted channel layer using theSiGe layer as a seed crystal in the peripheral circuit area.

In this case, a distortion impressed semiconductor layer, for example, aSiGe layer 32 with a Ge concentration of 20˜30%, is formed via theporous Si layer on the seed substrate, the SiGe layer 32 in the displayarea is etched after bonding and separation of the seed substrate inorder to expose the SiO₂ layer 36 a of the insulating layer, a poly-Silayer 14 in the display area is formed by Si epitaxial growth by CVD,and a distorted Si layer 12 b is formed as a distorted channel layerusing the SiGe layer 32 as a seed crystal in the peripheral circuitarea.

Furthermore, a distortion impressed semiconductor layer, for example, aSiGe layer 32 with a Ge concentration of 20˜30%, is formed via theporous Si layer on the seed substrate, the SiGe layer 32 in the displayarea is etched after bonding and separation of the seed substrate inorder to expose the SiO₂ layer 36 a of the insulating layer, a lightshielding metallic layer is formed in the display device forming region,an insulating layer is formed on it [metallic layer], a poly-Si layer 14is formed in the display area by CVD, and a distorted Si layer 12 b isformed as a distorted channel layer using the SiGe layer 32 as a seedcrystal in the peripheral circuit area.

In this case, it is desirable that the composition ratio of Ge isgreater: 0.3: desirable ratio, 0.2 or lower: there is no significantimprovement in the mobility of MOSTFT, 0.5 or greater: there areproblems with increased surface roughness of the SiGe layer and reducedfilm quality.

A gradation composition is applied wherein the Ge concentration slowlyincreases in the SiGe layer and a desirable concentration is achieved onthe surface. It is desirable to form a distorted Si layer 12 b as adistorted channel layer on the SiGe layer with a gradation composition.

In the execution form mentioned above, a poly-Si layer is formed in thedisplay area to form a poly-Si TFT section. However, an amorphous Silayer or amorphous/poly mixed Si layer or a poly-Si layer can be formedby plasma CVD, thermal CVD, sputtering or vapor deposition to form anamorphous Si TFT or an amorphous/poly mixed Si TFT or a poly-Si TFTsection.

Also, as in (A), it is possible that at least one of the group IVelements including Ge, Sn, Pb, is added in an proper quantity (a totalof 1×10¹⁷ ˜1×10²² atoms/cc, preferably 1×10¹⁸ ˜1×10²⁰ atoms/cc) to theamorphous Si layer or an amorphous/poly mixed Si layer or a poly-Silayer 14, and a poly-Si film is re-crystallized by said solid phasedeposition or flash lamp annealing, pulsed or continuous wave laserannealing, or condensing lamp annealing to form a poly-Si TFT section.

As a result, the irregularities present in the crystalline grain fieldof the poly-Si film (Grain boundary) are reduced and the film stress isreduced to achieve a poly-Si TFT with a high carrier mobility and highquality.

These group IV elements can be implanted in the amorphous Si film oramorphous and poly mixed Si layer or poly-Si layer by ion implantationor ion doping.

Alternatively, the group IV elements including Ge, Sn, etc. in arbitraryconcentrations can be mixed as a gaseous component in the raw materialgas when performing a CVD process such as Si epitaxial growth, plasmaCVD or thermal CVD to be implanted in the amorphous Si or amorphous andpoly mixed Si layer or poly-Si layer.

An amorphous Si or amorphous and poly mixed Si layer or poly-Si layercontaining the group IV elements including Ge, Sn, etc in arbitraryconcentrations can be formed by sputtering Si target layers containingthe group IV elements including Ge, Sn, etc.

(7) An ultra slim TFT substrate layer is prepared by a generaltechnology by forming a poly-Si TFT section 15 a as a display deviceunit (See FIG. 22 (a)) and wirings on the surface layer of a poly-Silayer 14 with a thickness of 50˜100 nm and with a controlled crystalgrain size, by forming a monocrystalline Si TFT section 15 b (See FIG.22 (b)) and any of or both of semiconductor devices and semiconductorfor integrated circuits such as diodes, resistors, capacitors and coils,as a peripheral circuit unit on the monocrystalline Si layer 12 b. Sincemonocrystalline Si layer 12 b has high electron and positive holemobility as well as a monocrystalline Si substrate, picture signalprocessing circuits, picture quality correction circuits, memorycircuits, CPU (central processing unit) circuits and DSP (digital signalprocessor) circuits can be incorporated as well as peripheral drivingcircuits.

The conditions [for preparation] are in compliance with (A).

At the same time, an external output electrode (including solder bumps),connected to peripheral circuits in the ultra slim TFT substrate layeris formed. In this case, it is desirable to make connections to aflexible board and mount on a PCB by means of anisotropic conductivefilm welding, ultrasonic welding or soldering after forming LCD panels.Diodes, resistors, capacitors, coils and wirings are not shown in thediagrams.

As a countermeasure against TFT leakage current by back reflection dueto strong incident light as in projectors, a light shielding metalliclayer 37 of transition metal silicides such as WSi2 (Tungsten silicide),TiSi2 (Titanium silicide), MoSi2 (molybdenum silicide) with a thicknessof 200˜300 nm is patterned by CVD below the poly-Si TFT section oramorphous Si TFT section 15 a. The pattern in the display area is shownin FIG. 23 (a) and the pattern in the peripheral circuit area is shownin FIG. 23 (b).

At this stage, it is desirable to form a groove 62 from themonocrystalline Si layer 12 b at least up to the high porous Si layer 34b along the division line that is a division boundary within the scribeline, when [the layer] is divided into single panels of various ultraslim electrooptic displays. By forming a groove 62, the ultra slim TFTsubstrate layer which will be discussed later is divided within thescribe line so that separation from the Si substrate 10 becomes easy anddivision in the subsequent processes can be performed easily.

A groove 62 is preferably formed with an arbitrary width from themonocrystalline Si layer 12 b at least till until the high porous Silayer 34 b by dry etching (plasma etching using SF₆, CF₄, Cl⁺ O₂,HBr+O₂, reverse sputter etching, etc.), wet etching (fluoric acidetchants such as HF+H₂O₂+H₂O mixed solution or HF+HNO₃+CH₃COOH mixedsolution, alkaline etchants), or mechanical processing (cutting a grooveusing a blade dicing diamond cutter, cemented carbide cutter, andultrasonic cutter).

A transparent resin 16 which is mounted in the pixel opening section isalso mounted in the groove to be able to reduce chipping, cracking andfracturing of the insulating layer and the monocrystalline Si layer 12 bwhen being separated.

(8) The poly-Si layer 14 at the pixel opening section in the displayarea is removed by etching. The conditions are in compliance with (A).

(9) A transparent insulating film with a thickness of 50˜200 nm (e.g.,SiO₂ layer 13 b, SiNx and SiO₂ laminated film, SiO₂, SiNx and SiO₂laminated film, SiON, etc.) and a light-shielding metallic film with athickness of 100˜300 nm (hereafter referred to as a metallic film) 17are formed respectively by CVD, sputtering or vapor deposition.Subsequently, connections of the poly-Si TFT section 15 a on the poly-Silayer 14 (drains, sources and gates), and the metallic film 17 at thebottom of the pixel opening sections are removed by etching, atransparent resin 16 is embedded in the pixel opening followed bysurface flattening by CMP (See FIG. 24). The conditions are incompliance with (A).

(10) A window is made in the transparent resin on the poly-Si TFTsection 15 a in the display area and a transparent electrode 18 a isformed as a pixel electrode which is made of ITO and IZO to form anultra slim TFT substrate layer (See FIG. 24).

The conditions are in compliance with (A).

As a countermeasure against TFT leakage current by strong incident lightas in projectors, a light shielding metallic layer 37 of transitionmetal layer is formed below the poly-Si TFT section or amorphous Si TFTsection 15 a in the display area as shown in FIG. 24. (b). The leakagelight can be completely shield by covering the upper section and lowersection of the poly-Si TFT section or amorphous Si TFT section 15 a inthe display area with a light shielding metallic layer 37, and ametallic film 17.

(11) An alignment process is applied by forming alignment films 20 a and20 b respectively for the support substrate 33 and the facing substrate21. A sealant and common [electrode] agents (not shown) are coated onone of [surfaces] and both substrates are laminated and sealed with aspecified liquid crystal gap of 2 μm.

The conditions are in compliance with (A).

(12) While the support substrate 33 and the facing substrate 21 arecovered at least with a antistatic UV tape 23, the support substrate 33is separated from the high porous Si layer 34 b by a high pressure fluidjet injection exfoliation method using a water jet, air jet or water/airjet, or laser process exfoliation method, or laser/water jet processexfoliation method (See FIG. 25). The conditions are in compliance with(A).

(13) The low porous Si layer 34 c, monocrystalline Si layer 35, SiO₂layer 36 a, and monocrystalline Si layer 32 at the side separated areetched to expose the transparent resin 16 in the display area via SiO₂layer 13 a and SiO₂ layer 13 b. The conditions are in compliance with(A).

In the cases shown in FIG. 21 (b) and (c), there is no need of etchingthe SiO₂ layer 36 a, and the monocrystalline Si layer 32.

The subsequent processes are all in compliance with descriptions in (A).

When producing ultra slim reflective type LCDs, said processes (1)˜(7)(FIGS. 17˜23) are the same.

Subsequently, as in the processes described in (A-2), a wiring layer 27is formed in the peripheral circuit area and a protective film 28 isformed, and a reflective electrode 19 a with a high reflectance isprepared from aluminum, aluminum alloys, silver, silver alloys, nickel,nickel alloys, titanium and titanium alloys to be connected at the drainof the TFT in the display area (See FIG. 26).

In the reflective electrode 19 a, an appropriate concave/convex shape isformed on the electrode in order to improve ease in seeing the displayby providing an appropriate light scattering effect in the case ofdirect-viewing reflective LCDs.

In the case of reflective LCDs for projectors, a flat electrode shape isdesirable.

Subsequently, an alignment film 20 a is formed, sealant and common[electrode] agents (not shown) are coated, a facing substrate 21 onwhich a transparent electrode 18 b and an alignment film 20 b are formedis laid and sealed with a specified liquid crystal gap of 2 μm.

The subsequent processes are same as those described in (A-2).

When producing ultra slim semi-transmissive type LCDs, said processes(1)˜(7) (FIGS. 17-23) are the same as those described for transmissivetype LCDs. The subsequent processes are same as those described in(A-3).

When producing ultra slim lower luminous type organic EL and ultra slimupper luminous type organic EL, said processes (1)˜(7) (FIGS. 17˜23) arethe same as those described for transmissive type LCDs. The subsequentprocesses are same as those described in (A-4) and (A-5).

According to the double porous Si layer separation method described inthis execution form, a SiO₂ layer 13 a is formed by thermal oxidation ofthe monocrystalline Si layer 32 of the support substrate 33; a SiO₂layer 13 a in the peripheral circuit area is removed while leaving theSiO₂ layer 13 a in the display area; a poly-Si layer 14 in the displayarea and a monocrystalline Si layer 12 b in the peripheral circuit areaare formed respectively by Si epitaxial growth such as CVD; ifdesirable, a poly-Si TFT section 15 a as a display device unit is formedin the poly-Si layer 14 in the display area wherein crystal grain sizes(electron and positive hole mobility) are controlled by flash lampannealing or solid phase deposition or laser annealing or condensinglamp annealing, and one or both of semiconductor devices andsemiconductor for integrated circuits such as monocrystalline Si TFTsection 15 b are formed as a peripheral circuit unit in themonocrystalline Si layer 12 b in the peripheral circuit area.

As a result, poly-Si TFT display devices with arbitrarily controlledelectron and positive hole mobility with low current leakage qualitiesand the monocrystalline Si TFT peripheral circuits with a high electronand positive hole mobility with a high drivability can be formed withinan ultra slim TFT substrate layer on the same Si substrate 33.Therefore, an ultra slim electrooptic display with a high electron andpositive hole mobility and low current leakage qualities can be producedwith high luminance, high resolution, and high functionality.

(26) Or with the separation method for another double porous Si layer inthe execution figure, the insulating layer of SiO₂ layer 36 a is exposedafter the display area of monocrystalline Si layer 32 of the supportsubstrate 33 is etched. The poly Si layer 14 in the display area and themonocrystalline Si layer 12 b in the peripheral circuit area are eachformed with semiconductor epitaxial growth. Because the poly SiTFT 15 aas the display area in the poly Si layer 14 of the display area, wherecrystal grain size (high electron and positive hole mobility) isarbitrarily controlled with such methods as flash lamp annealing methodor solid phase deposition method or laser annealing method or condensinglamp annealing method, etc., as required, and either the semiconductordevice or the semiconductor for integrated circuits of themonocrystalline SiTFT area 15 b, etc., as the peripheral circuit in themonocrystalline Si layer 12 b or both are formed, the poly SiTFT displayelement, which has arbitrarily controlled relatively low high electronand positive hole mobility and low electric current leakage qualities,and the monocrystalline SiTFT peripheral circuit which has high electronand positive hole mobility and high drivability, are formed inside theultra slim TFT substrate layer of the same support substrate 33. Withthis process, you can achieve an ultra slim electrooptic display deviceunit which has high electron and positive hole mobility and lowelectronic current leakage qualities, and which has high intensity, highdefinition and is sophisticated.

Or, with this separation method of even another double porous Si layerin this execution figure, the insulating layer of SiO₂ layer 36 a isexposed after the display area of monocrystalline Si layer 32 of thesupport substrate 33 is etched. The light shielding metallic layer isformed on the poly SiTFT forming area of SiO₂ layer 36 of the displayarea by CVD and etching. The insulating layer is formed on top of it.The poly Si layer 14 is formed through the insulating layer in thedisplay area and the monocrystalline Si layer 12 b is formed in theperipheral circuit area with semiconductor epitaxial growth. Because thepoly SiTFT part 15 a as the display area in the poly Si layer 14 of thedisplay area, where crystal grain size (high electron and positive holemobility) has been arbitrarily controlled with such as flash lampannealing method or solid phase deposition method or laser annealingmethod or condensing lamp annealing method, etc., as required, andeither the semiconductor device or the semiconductor for integratedcircuits of monocrystalline SiTFT area 15 b, etc., as the peripheralcircuit in the monocrystalline Si layer 12 b, or both are formed, thepoly SiTFT display element, which has arbitrarily controlled relativelylow high electron and positive hole mobility and low electric currentleakage qualities, and the monocrystalline SiTFT peripheral circuit,which has high electron and positive hole mobility and high drivability,are formed inside the ultra slim TFT substrate layer of the same supportsubstrate 33. With this process, an ultra slim electrooptic displaydevice unit which has high electron and positive hole mobility and lowelectronic current leakage qualities, and which is high intensity, highdefinition and sophisticated can be obtained.

If the poly Si layer 14 of the display area mentioned above contains aproper quantity (for example, a total of 1017-1022 atom/cc, preferably1018-1020 atom/cc) from ion implantation or ion doping, etc. of leastone kind of group IV elements of Ge, Sn, Pb, etc. selectively, and thepoly SiTFT display element of the poly Si film, which arbitrarilycontrolled the crystal grain size selectively with solid phasedeposition method, flash lamp annealing method, pulse condition orContinuous wave laser annealing method, or condensing lamp annealingmethod, etc. with this circumstance, is made, the irregularities whichexists in the crystal grain boundary (grain boundary) of that poly Sifilm decrease and the film stress is decreased and the poly SiTFT withhigh carrier mobility and high quality can be easily obtained. And thepoly SiTFT display element, which arbitrarily controlled relatively lowhigh electron and positive hole mobility and low electric currentleakage qualities, can be obtained.

Furthermore, the poly Si layer which contains at least one kind of groupIV elements Sn, Ge, Pb, etc., is formed in the aforementioned displayarea with semiconductor epitaxial growth. If we have a poly SiTFTdisplay element of the poly Si layer which selectively controlled thecrystal grain size with solid phase deposition method, flash lampannealing method, pulse condition or Continuous wave laser annealingmethod, condensing lamp annealing method, etc., the irregularity whichexists in the grain boundary of the poly Si film is decreased and polySiTFT with high carrier mobility and high quality is likely to beobtained due to a decrease in the film stress. And you can obtain thepoly SiTFT display element which has relatively low high electron andpositive hole mobility that is arbitrarily controlled, and low electriccurrent leakage qualities.

Or, the separation method for the double porous Si layer in thisexecution figure, SiO₂ Layer 13 a is formed by thermal oxidizing themonocrystalline Si layer 32 of the support substrate 33. The amorphousSi film or the amorphous and the poly mixture Si film or the poly Sifilm 14 are formed with Plasma CVD, heat CVD, sputtering, evaporation,etc., the monocrystalline Si film is exposed by etching the amorphous Sifilm or the amorphous and the poly mixture Si film or poly Si film 14and SiO₂ layer 13 a. Because the amorphous Si film of the display areawhich controlled the crystal grain size arbitrarily with flash lampannealing or solid phase deposition method or laser annealing method orcondensing lamp annealing method, etc. according to the needs, or theamorphous and the poly mixture Si film or the amorphous SiTFT part 15 aas display element part in the poly Si layer 14 or the amorphous and thepoly mixture SiTFT or poly SiTFT part 15 a, either the semiconductordevice or the semiconductor for integrated circuits of monocrystallineSiTFT area 15 b, etc. as the peripheral circuit in the monocrystallineSi layer 12 b of the peripheral circuit are, or both are formed, anultra slim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities, andwhich is high intensity, high definition and is sophisticated can beobtained by forming the amorphous SiTFT or the amorphous and the polymixture SiTFT or the poly SiTFT display element which has relatively lowhigh electron and positive hole mobility and low electric currentleakage qualities which is controlled optionally, and themonocrystalline SiTFT peripheral circuit which has high electron andpositive hole mobility and high drivability are formed inside the ultraslim TFT substrate layer of the same support substrate 33.

Or, with the separation method for another double porous Si layer inthis execution figure, the display area of monocrystalline Si layer 32of the support substrate 33 is etched and the insulating layer of SiO₂Layer 36 a is exposed. The insulating layer, the amorphous Si film orthe amorphous and the poly mixture Si film or the poly Si film 14 areformed with Plasma CVD, heat CVD, sputtering, evaporation, etc. Becausethe poly Si layer in the display area or the amorphous Si film or theamorphous and the poly mixture Si film 14, which controlled the crystalgrain size arbitrarily with flash lamp annealing or solid phasedeposition method or laser annealing method or condensing lamp annealingmethod, etc. according to the need, as the display element the poly Silayer of the display area or the amorphous Si film or the amorphous andthe poly mixture Si film 14 or the amorphous and the poly mixture SiTFTor poly SiTFT part 15 a, either the semiconductor device and thesemiconductor for integrated circuits of monocrystalline SiTFT area 15b, etc. as the peripheral circuit in the monocrystalline Si layer 12 bof the peripheral circuit area, or both are formed, an ultra slimelectrooptic display device unit, which has high electron and positivehole mobility and low electric current leakage qualities, and which ishigh intensity, high definition and sophisticated, can be obtained afterforming the amorphous SiTFT or the amorphous and the poly mixture SiTFTor the poly SiTFT display element, which has relatively low highelectron and positive hole mobility and low electric current leakagequalities which is controlled optionally, and the monocrystalline SiTFTperipheral circuit which has high electron and positive hole mobilityand high drivability, inside the ultra slim TFT substrate layer of thesame support substrate 33.

Or, with the separation method for even another double porous Si layerin this execution figure, the display area of monocrystalline Si layer32 of the support substrate is etched and the insulating layer of SiO₂layer 36 a is exposed. The light shielding metallic layer is formed byetching and CVD in the pixel display element forming area of SiO₂ layer36 a of the display area. The insulating layer and the amorphous Si filmor the amorphous and the poly mixture Si film or the poly Si layer 14are formed extensively with plasma CVD, heat CVD, sputtering andevaporation, etc. The poly Si layer of the display area, which thecrystal grain size (high electron and positive hole mobility) isarbitrarily controlled with flash lamp annealing method or solid phasedeposition method or laser annealing method or condensing lamp annealingmethod, etc., or the amorphous Si layer or the amorphous and the polymixture Si layer 14, the amorphous SiTFT as the display element or theamorphous and the poly mixture SiTFT or the poly SiTFT 15 a, and eithersemiconductor element such as monocrystalline SiTFT 15 b as theperipheral circuit in the monocrystalline Si layer 12 b which has etchedthe insulating layer and the amorphous Si layer or the amorphous or thepoly mixture Si layer or the poly Si layer 14 or semiconductorintegrating circuit or both are formed. Because of this process, thereflected light is blocked from the back by the light shielding metalliclayer and the amorphous SiTFT or the amorphous and the poly mixtureSiTFT or the poly SiTFT display element, which has relatively low highelectron and positive hole mobility and low electric current leakagequalities that is controlled optionally, and the monocrystalline SiTFTperipheral circuit, which has high high electron and positive holemobility and high drivability, are formed inside the ultra slim TFTsubstrate layer of the same support substrate 33. A high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities can be obtained.

The amorphous Si layer or the amorphous and the poly mixture Si layer orthe poly Si layer 14 in the display area mentioned above, contains theproper quantity (for example, total of 10¹⁷˜10²² Atom/cc, preferably10¹⁸˜10²⁰ Atom/cc) at least one kind of group IV elements such as Ge(germanium), tin, lead, etc., from ion implantation or selective iondoping, if we selectively make the poly SiTFT display element of thepoly Si film which is controlled the crystal grain size arbitrarily bythe aforementioned process, using the solid phase deposition method, theflash lamp annealing method, the pulse condition or the Continuous wavelaser annealing method and the condensing lamp annealing method withthis circumstance, the irregularity which exists in the grain boundaryof the poly Si film is decreased, and the poly SiTFT of high carriermobility of high quality is likely to be obtained. And the poly SiTFTdisplay element with high electron and positive hole mobility which isarbitrarily controlled and with low electric current leakage qualitiesand the monocrystalline semiconductor TFT peripheral circuit with highelectron and positive hole mobility and with high drivability are formedon the same support substrate.

Furthermore, the amorphous Si layer or the amorphous and the polymixture Si layer or the poly Si layer 14 which contains at least onekind of group IV elements such as tin, germanium, lead, etc., are formedin the aforementioned display area with plasma CVD, heat CVD,sputtering, and evaporation. If we have the poly SiTFT display elementof the poly Si layer which controlled the crystal grain size arbitrarilywith solid phase deposition method, flash lamp annealing method, laserannealing method and condensing lamp annealing method, the poly SiTFTwith high carrier mobility and high quality can be obtained easilybecause the irregularity which exists in the crystal grain boundary ofthe poly Si film, and the stress of the film are decreased. And the polySiTFT display element with high electron and positive hole mobilitywhich is arbitrarily controlled and with low electric current leakagequalities and the monocrystalline semiconductor TFT peripheral circuitwith high electron and positive hole mobility and with high drivabilityare formed on the same support substrate.

By the way, with the separation method for the double porous Si layer inthis execution figure, SiGe layer 32 with a Ge density of 20˜30% isformed on the seed substrate as a distortion impression semiconductorlayer through the porous Si layer, the SiO₂ Layer 13 a is formed withthermal oxidizing after attaching and the separating the seed substrate.The SiO₂ Layer 13 a in the peripheral circuit area is removed whileleaving the SiO₂ Layer 13 a in the display area. The poly Si layer 14may be formed in the display area with the epitaxial growth such as CVD,etc., the SiGe layer 32 as distortion impression semiconductor layer maybe formed in the peripheral circuit area, and distortion Si layer 12 bas distortion channel layer in the seed substrate.

In addition, the SiGe layer 32 with a Ge density of 20% is formed as thedistortion impression semiconductor layer through the porous Si layer,SiO₂ layer 36 a in the insulating layer is exposed by etching SiGe layer32 in the display area and after attaching and separating the seedsubstrate. The poly Si layer 14 in the display area may be formed withsemiconductor epitaxial growth such as CVD, SiGe layer 32 may be formedas distortion impression semiconductor layer in the peripheral circuitarea in the seed, distortion Si layer 12 b as distortion channel layermay be formed.

Furthermore, SiGe layer 32 with a Ge density of 20% is formed as thedistortion impression semiconductor layer through the porous Si layer onthe seed substrate. The light shielding metallic layer in the displayforming element area is formed by etching the SiGe layer 32 in thedisplay area and the SiO₂ layer 36 a in the insulating layer is exposedafter attaching and separating seed substrate. The insulating layer isformed on top of it, and the poly Si layer 14 may be formed in thedisplay area with semiconductor epitaxial growth such as CVD, the SiGelayer 32 may be formed in the seed substrate as a distortion impressionsemiconductor layer in the peripheral circuit area, distortion Si layer12 b as distortion channel layer may be formed.

Because of this, the monocrystalline SiMOSTFT peripheral circuit isachieved by accomplishing the improvement of greater electronic mobilitywith approximately 1.76 times higher drivability compared to themonocrystalline Si layer of non-distortion channel layer in the past andyou can obtain the ultra slim electrooptic display device unit with thehigh performance, high definition and high quality compared to the past.

(C) Separation Method for Ion Implantation Layer

I will explain the manufacturing method for the ultra slim electroopticdisplay device unit with the ion implantation layer method for chemicalseparation the uses an ion implantation layer with these executionfigures. FIG. 27 to FIG. 30 shows a manufacturing process for the ultraslim type LCD of the separation method with the hydrogen ionimplantation layer in the implementation of this invention.

The support substrate 40 which consists of the monocrystalline Si ismade with thermal oxidizing and the SiO₂ layer 13 a is formed. The SiO₂layer in the peripheral circuit area is removed by etching, leaving theSiO₂ layer 13 a in the display area. The poly Si layer 14 in the displayarea is formed, and the monocrystalline Si layer 12 b Si formed in theperipheral area are each formed with semiconductor epitaxial growth suchas CVD. Each condition at this time corresponds to (A). A SiGe layerwith a Ge density of 20˜30% is formed on the surface of the supportsubstrate 40 as a distortion impression semiconductor layer withsemiconductor epitaxial growth such as CVD, the SiO₂ layer 13 a isformed by thermal oxidizing. The SiO₂ layer 13 a in the peripheralcircuit area is removed by etching, leaving the SiO₂ layer 13 a in thedisplay area. The poly Si layer 14 in the display area may be formedwith semiconductor epitaxial growth such as CVD, distortion impressionsemiconductor layer of the SiGe layer may be formed in the peripheralcircuit area, the distortion Si layer 12 b of the distortion channellayer may be formed in the seed substrate.

(A) Corresponds to the conditions to arbitrarily control the crystalgrain size in the poly Si layer 14 in the display area with flash lampannealing or solid phase deposition method or laser annealing method orcondensing lamp annealing method, etc. as required.

In the mean time, the support substrate 40 uses not only themonocrystalline Si substrate formed with CZ (Czochralski) law, MCZ(Magnetic field Applied Czochralski) law, FZ (Floating Zone) low, etc.,but also uses the monocrystalline Si substrate on which the surface ofthe substrate has had hydrogen anneal processing or the epitaxialmonocrystalline Si substrate, etc. Of course, instead of themonocrystalline Si substrate, the monocrystalline SiGe substrate, orfurthermore a monocrystalline compound semiconductor substrate such asSiC substrate, GaAs substrate and Inp substrate, etc. can be used.

(2) You can achieve whether or both the poly SiTFT area 15 a (pleaserefer the FIG. 28 (a)) as the display element area in the poly Si layer14 with general purpose technology, wiring, etc., or the semiconductorelement such as the monocrystalline SiTFT area 15 b (please refer theFIG. 28 (a)) etc. as the peripheral circuit area in the monocrystallineSi layer 12 b or the semiconductor for integrated circuits. Thiscorresponds to conditions (A).

Furthermore, because the monocrystalline Si layer 12 b has high electronand positive hole mobility the same as the Si substrate, not onlyperipheral driver circuitry but also the image signal processingcircuit, the picture quality compensation circuit, the memory circuit,the CPU (Central Processing Unit) circuit, the DSP (digital SignalProcessor) circuit, etc. can be included. This condition corresponds to(A). Meanwhile, the illustration is abbreviated for the diode,resistance, capacitor, coil, wiring, etc.

(3) The hydrogen ion implantation layer 41 is formed extensively.Meanwhile, the hydrogen ion dose quantity is approximately 1000 keV,5×10¹⁶˜1×10¹⁷ atoms/cm² and a of depth 10 μm is filled.

At this time, in order to equalize the high density hydrogen ion filllayer 41 inside the monocrystalline Si substrate, and in order toprevent the high density hydrogen ion separation, the high densityhydrogen ion implantation layer 41 is formed after the process at morethan 500° C.

However, because the electrode, wiring, etc. can become the cause of thehydrogen ion fill depth dispersion, it is desirable to form these beforeor after the exfoliation annealing and after the hydrogen ionimplantation process.

(6) Process for the Anneal Processing for Exfoliation

The annealing for exfoliation with heat treatment at 400˜600° C., for10˜20 minutes, or the rapid heating rapid cooling of RTA (Rapid ThermalAnneal), for example halogen lamp with 800° C. for several seconds, orXe flash lamp annealing at 1000° C. for several seconds, with heattreatment such as laser ablation of the carbonic dioxide, etc.

Because of this, the hydrogen ion implantation which was filled expandsin the distortion layer 41 a (please refer FIG. 29) in the hydrogen ionimplantation layer 41 because of pressure action and the crystalre-arranges inside the micro bubbles. However, the device structurelayers, such as silicon oxide film, silicon nitride film exist on thesupport substrate 40, and it penetrates these, and the hydrogen ionimplantation layer under the insulating film is formed and it generatesthe distortion due to heat treatment.

But, in case where the electrode and the wiring formation is done beforethe exfoliation annealing, it is even more desirable to do theexfoliation annealing with the TRA of rapid heating rapid cooling withcooling of the ultra slim TFT substrate layer side of the back of thesupport substrate (monocrystalline Si substrate 40 through the UV tapewith support jig which is liquid cooled).

Or, it is desirable to do the laser processing exfoliation method whichis done with the hydrogen ion implantation layer 41 without theexfoliation annealing, or the laser water jet process exfoliation methodand cooling the ultra slim TFT substrate layer side through the UV tapeby the support jig with liquid cooling.

At this stage, it is desirable to form the groove 62 from themonocrystalline Si layer 14 to at least the distortion area 41 a of thehydrogen ion implantation layer along with the dividing lines to dividethe assembly into one panel each of ultra slim electrooptic displaydevice units afterwards, in other words along with the dividing boundaryline inside the scribe line. By forming the groove 62, it is possible toseparate from the support (Si) substrate 40 easily, and at the same timeto divide the process which will be mentioned later, because the ultraslim TFT substrate layer which will be mentioned later is divided insidethe scribe line beforehand.

It is better to form the groove 62 at least to the distortion layer 41 aof the hydrogen ion implantation layer with dry etching (plasma etchingand opposite sputter etching, etc. with compounds such as SF₆, CF₄,Cl+O₂, HB r+O₂, etc.), wet etching (such as hydrofluoric acid etchant,alkaline etchant with mixed liquid HF+H₂O₂+H₂O, mixed liquid HF+HNO₃+CH₃COOH, etc.), mechanical processing (cutting the groove by the bladedicing, the diamond cutter, the cemented carbide cutter, the ultrasoniccutter etc.).

(7) The poly Si layer 14 of the pixel opening section in the displayarea is removed by etching. This corresponds to condition (A).

(8) The transparent insulating film (for example, SiO₂ layer 13 b, SiNxand SiO₂, laminating film, SiON, etc.) with 50˜200 nm thickness and thelow reflective metallic film with 100˜300 nm thickness are formed byCVD, sputtering, vapor deposition method, etc. in order, the metallicfilm 17 of the connection part of the poly SiTFT area on top of the polySi layer 14 and the bottom of pixel opening section are etched, and thetransparent resin 16 and the like are embedded inside the pixel openingsection, and the surface is planarized with CMP, etc. This correspondsto condition (A).

(9) The transparent resin 16 on the poly SiTFT area 15 a drain in thedisplay area is done by opening the window, the ultra slim TFT substratelayer is formed (please refer the FIG. 29) by forming the transparentelectrode 18 a, etc. as the pixel electrode such as ITO, IZO, etc. Thiscorresponds to condition (A). However, when the wiring and the externaloutput electrode (includes solder bump) inside the peripheral circuit ofthe ultra slim electrooptic display element substrate layer is formed atthe same time, it is desirable to connect with the flexible substrateand mount to a PCB with such as an anisotropic electric conduction filmconnection, an ultrasonic connection and solder.

(10) The alignment layer 20 a and 20 b are each formed on the supportsubstrate 40 and the facing substrate 21, and the orientation treatmentis also done, and with the sealing medicine and the common agents (notin the figure) on either one, it seals with the specified liquid crystalgap, for example 2 μm by laminating (please refer the FIG. 30). Thiscorresponds to condition (A).

(11) The tops of the support substrate 40 and the facing substrate 21are covered with the UV tape 23, etc. with at minimum electrostaticprevention which has the least sealant transfer, the support substrate40 is separated from the distortion layer 41 a of the hydrogen ionimplantation layer 41 (please refer FIG. 30). This corresponds tocondition (A).

Although the pulling exfoliation is done after the exfoliation annealingdiscussed above, it is OK to do the high pressure fluid jet injectionexfoliation after sealing the support substrate 40 and the facingsubstrate 21 by laminating.

Furthermore, the hydrogen ion implantation layer 41 is heated partiallywith the laser processing exfoliation method or the laser water jetprocess exfoliation method and then, it is acceptable to do thedistortion and exfoliate. This corresponds to condition (A).

In other words, the high density hydrogen, which was filled with ions bylocal heating due to the laser processing exfoliation method, isexpanded by the heat as the facing substrate 21 side is cooled throughthe UV tape by the supporting jig which is liquid cooled as required.The support substrate is separated by producing the distortion layer 41a in the hydrogen ion implantation layer 41 by pressure action insidethe micro bubbles and the crystal re-arranging action.

Meantime, cooling the side of the facing substrate 21 via a UV tapeusing a support jig which is liquid cooled is not always necessarybecause the in the laser water jet process exfoliation method, the waterthat is irradiated with the laser provides cooling action at the sametime.

(12) The hydrogen ion implantation layer (monocrystalline Si layer) 41of the separated surface is etched, the transparent resin 16 which wasembedded to the pixel opening section of the display area through theSiO₂ layer 13 a and the SiO₂ layer 13 b is exposed. This corresponds tocondition (A).

The process described in the following corresponds to (A).

In the mean time, when the reflective type LCD, the semi-transmissivetype LCD, the underside luminous type organic EL and the surfaceluminous type organic EL are manufactured, the process for (1)˜(4) isdone with the same process as a transmissive type LCD, the process foreach is the same process described in the following (A˜2), (A˜3), (A˜4)and (A˜5).

Although, for this execution figure, hydrogen ions are used forseparation, it is possible to use a noble gas such as nitrogen andhelium, etc. in the place of the hydrogen ions.

For example, in case of hydrogen ion implantation, rather than using theion implantation unit (same as the traditional ion implantation devicewhich fills an impurity such as boron or phosphorus to the Si substrate)which does the mass separation of the hydrogen ion beam and scans, youcan use the hydrogen negative ion beam fill device which creates theplasma includes hydrogen by plasma production method in which thehydrogen negative ion beam is pulled out from this plasma, and whichfills with hydrogen negative ions to the specified depth.

Like mentioned above, with the separation method for the ionimplantation layer in the execution form, the surface of supportsubstrate 40 which consists of the monocrystalline Si is thermaloxidized and the SiO₂ layer 13 a is formed. The SiO₂ layer 13 a in theperipheral circuit area is removed leaving the SiO₂ layer 13 a in thedisplay area. The poly Si layer 14 in the display area and themonocrystalline Si layer 12 b in the peripheral circuit area are eachformed with Si epitaxial growth. The poly SiTFT area 15 a as the displayelement in the poly Si layer 14 in the display area, which arbitrarilycontrolled the crystal grain size (electronic positive hole mobility),and the monocrystalline SiTFT area 15 b as the peripheral circuit areain the monocrystalline Si layer 13 a of the peripheral circuit area areeach formed with methods such as solid phase deposition method, flashlamp annealing method, laser annealing method and condensing lampannealing method as required. The poly SiTFT display element, which haslow high electron and positive hole mobility that was arbitrarilycontrolled, and low electric current leakage qualities, and themonocrystalline SiTFT peripheral circuit, which has high electron andpositive hole mobility and high drivability, are formed inside the ultraslim TFT substrate layer on the same support substrate 40. A highintensity, high definition and sophisticated ultra slim electroopticdisplay device unit which has high electron and positive hole mobilityand low electric current leakage qualities can be obtained.

Furthermore, the poly Si layer 14 in the display area contains theproper quantity (for example, a total of 10¹⁷˜10²² Atom/cc, preferably10¹⁸˜10²⁰ Atom/cc) of a minimum of one kind of group IV elements of Ge,Sn, Pb, etc. as required with ion implantation or ion doping or CVD,etc. in the deposition layer. And by maintaining this condition, if wehave the poly SiTFT display element of the poly Si film which hasarbitrarily controlled crystal grain size with solid phase depositionmethod, flash lamp annealing method, pulse condition or Continuous wavelaser annealing method or condensing lamp annealing method, etc., theirregularity which exists in the crystal grain boundary of the poly Sifilm is decreased, and the film stress is decreased, it is easy toobtain the display area of the poly SiTFT with high carrier mobility andhigh quality. The poly SiTFT display element, which has high electronand positive hole mobility that was arbitrarily controlled and lowelectric current leakage qualities, and the monocrystalline SiTFTperipheral circuit which has high electron and positive hole mobilityand high drivability are formed inside the ultra slim TFT substratelayer on the same support substrate 40. A high intensity, highdefinition and sophisticated ultra slim electrooptic display device unitwhich has high electron and positive hole mobility and low electriccurrent leakage qualities can be obtained.

Furthermore, the insulating layer SiO₂ layer 13 a and the amorphous Silayer or the amorphous and the poly mixture Si layer or the poly Silayer 14 are formed on the monocrystalline Si layer 12 a of the Sisubstrate 10 with plasma CVD, heat CVD, sputtering, evaporation, etc. Aminimum of the amorphous Si layer of the peripheral circuit area or theamorphous and the poly mixture Si layer or the poly Si layer 14 areremoved while leaving the SiO₂ layer 13 a of the display area and theamorphous Si layer or the amorphous and the poly mixture Si layer andthe poly mixture Si layer and the poly Si layer 14. Because theamorphous SiTFT or the amorphous and the poly mixture SiTFT or the polySiTFT area 15 a as the display element in the display area, and themonocrystalline SiTFT 15 b as peripheral circuit in the monocrystallineSi layer 12 b of the peripheral circuit area are each formed, theamorphous SiTFT which has relatively low high electron and positive holemobility and low electric current leakage qualities, or the amorphousand the poly mixture SiTFT or the poly SiTFT display element, and themonocrystalline SiTFT peripheral circuit which has high electron andpositive hole mobility and high drivability, are formed inside the ultraslim TFT substrate layer on the same Si substrate 40. A high intensity,high definition and sophisticated ultra slim electrooptic display deviceunit which has high electron and positive hole mobility and low electriccurrent leakage qualities can be obtained.

The amorphous Si layer or the amorphous and the poly mixture Si layer orthe poly Si layer 14 in the display area mentioned above contain theproper quantity (for example, a total of 10¹⁷˜10²² Atom/cc, preferably10¹⁸˜10²⁰ Atom/cc) of at least one kind of group IV elements of Ge, Sn,Pb, etc. as required, with ion implantation or ion doping or CVD, etc.forming a film. Maintaining this condition, if we have the poly SiTFTdisplay element of poly Si film which has re-crystallized the crystalgrain size with solid phase deposition method, flash lamp annealingmethod, pulse condition or Continuous wave laser annealing method,condensing lamp annealing method, etc., for example the irregularitywhich exists in the crystal grain boundary of the poly Si film isdecreased, and the film stress is decreased, it is easy to obtain thedisplay area of the poly SiTFT with high carrier mobility and highquality.

And the poly SiTFT display element which has relatively low highelectron and positive hole mobility and low electric current leakagequalities, and the monocrystalline SiTFT peripheral circuit which hashigh electron and positive hole mobility and high drivability, areformed inside the ultra slim TFT substrate layer on the same supportsubstrate 40. A high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities can beobtained.

Also, with this separation method for the ion implantation layer in thisexecution form mentioned above, the SiGe layer with a Ge density of20˜30% as distortion impression semiconductor layer is formed on thesurface of the support substrate which consists of the monocrystallineSi layer, the SiO₂ layer 13 a is formed by thermal oxidizing, the SiO₂layer 13 a in the peripheral circuit area is removed while leaving theSiO₂ layer 13 a in the display area. The poly Si layer 14 in the displayarea, the distortion impression semiconductor layer of the SiGe layer inthe peripheral circuit area, and the distortion Si layer 12 b as thedistortion channel layer in the seed may be formed with Si epitaxialgrowth such as CVD.

Because of this, if the distortion channel semiconductor layer isdistorted, the band structure is changed. As a result, the degeneracy isalleviated. Because the electron hole mobility can be increased, forexample when compared to the monocrystalline Si layer in thenon-distortion channel layer, approximately 1.76 times higher electronmobility can be actualized. A high performance, high definition andsophisticated ultra slim electrooptic display device unit, whichconsists of the display area, and the peripheral circuit of MOSTFT,which has high electron and positive hole mobility and high drivability,is possible.

(D) The Separation Method for Double Ion Implantation Layer

With this execution form, I will explain about the manufacturing methodfor the ultra slim electrooptic display device unit by the separationmethod for the double ion implantation layer (the semiconductor seedsubstrate is separated from the ion implantation layer which forms inthe semiconductor seed substrate, the semiconductor support substrate isseparated form the ion implantation layer which forms in thesemiconductor support substrate) which used the ion implantation layer.From FIG. 31 to FIG. 36 explains the process for the manufacturing ofultra slim LCD by the exfoliation method for double hydrogen ionimplantation exfoliation with the execution form of this invention.

(1) The hydrogen ion implantation layer 44 is formed by filling the highdensity hydrogen ion to the seed substrate 43, for example 12 inch Φ . .. with 1.2 mm thickness, which consists of monocrystalline Si. In themean time, the hydrogen ion can be filled with the doze quantityapproximately 300 Kev, 5×10¹⁶˜1×10¹⁷ Atoms/cm² and approximately 3 μmdepth (please refer the FIG. 31).

At this time, the monocrystalline Si layer 44 of SiGe layer with a Gedensity of 20˜30% as the distortion impression semiconductor layer maybe formed with Si epitaxial growth such as CVD on the surface of themonocrystalline Si substrate 43, so that exfoliated hydrogen ionimplantation layer (monocrystalline Si layer) 44 can become a distortionimpression semiconductor layer. And by filling with high densityhydrogen ion, as mentioned before, to this thickness (depth), thehydrogen ion implantation layer can be created.

At this time, the surface of the monocrystalline Si layer 44, whichafter the seed substrate separation is a distortion impressionsemiconductor layer, is set to become the desired density by making theangle structure where the Ge density becomes the desired density atdistortion layer 44 a of the hydrogen ion implantation layer in SiGelayer. It is desirable to form the monocrystalline Si layer 44, which isthe distortion impression semiconductor layer of the SiGe layer in thisangle structure, in the seed, and the distortion Si layer 12 b as adistortion channel layer by Si epitaxial growth.

In other words, it is desirable to make the surface density of themonocrystalline SiGe layer 44 which is a distortion impressionsemiconductor layer and is formed after the seed substrate separation,become a desired density by gradient constituting which makes the Gedensity a desired density in the distortion layer 44 of the hydrogen ionimplantation layer in the SiGe layer, and the monocrystalline Si layer44, which is a distortion impression semiconductor layer of the SiGelayer in this gradient constituting is formed in the seed and thedistortion Si layer 12 b as a distortion channel layer by the Siepitaxial growth.

Or, the monocrystalline Si substrate itself may make the monocrystallineSi substrate 43 which consists of SiGe with a Ge density 20˜30%.

(2) The support substrate 40 with for example, 12 inch Φ. 1.2 mmthickness, which consists of the monocrystalline Si, is oxidized withheat. The insulating layer which consists of the SiO₂ layer or Si₃N₄ andSiO₂ laminating film is formed (please refer FIG. 31).

By forming and thermal oxidizing the silicon nitride film or the siliconnitride film and the silicon oxide film on the monocrystalline Si layer40 other than the silicon oxide film SiO₂ with thermal oxidation, theinsulating film 42 may become a silicon oxide film and the laminatingfilm of silicon nitride film, or silicon oxide film, silicon nitridefilm and laminating film of silicon oxide film (for example SiO₂; 200nm, Si₃N₄; 50 nm and SiO₂; 200 nm) by the vacuum heat CVD.

Furthermore, it may become the silicon oxy-nitride film (SiON). Themonolayer film which is mentioned above and the insulating film ofmultilayer film may be formed with plasma CVD method, sputtering method,MBE method, vapor deposition method, etc.

(3) Attaching the Seed Substrate 43 and the Support Substrate 40.

After washing the support substrate 40 and the seed substrate 43, thehydrogen ion implantation layer 44 is joined to the surface ofinsulating layer 42 of the support substrate 40 at room temperature, andis connected with Van Del Waals power. After this process, heattreatment for 30 minutes with 400° C. for covalent bonding makes theattachment stronger. It is necessary to set the heat processing at thistime with a processing temperature and a processing time below thehydrogen ion separation temperature. The heat processing is same processexplained as (B) except for the processing temperature and theprocessing time.

Or, prior to this the, connecting surface is irradiated with an inertgas ion beam or an inert gas high-speed atomic beam such as argon in thevacuum at room temperature. The dust and soiling adhesion, etc. on thesurface is removed by sputter etching. You can make the bonding strongerby increasing the adhesion and increasing the surface unevenness inorder to join the surfaces.

(4) The high density hydrogen which is filled with ions is made toexpand with heat from the annealing for exfoliation. The distortionlayer 44 a is generated in the hydrogen ion implantation layer 44 by thepressure inside the micro bubbles and by crystal re-arrangement action.UV tape 23 is attached on both of the seed substrate 43 and the supportsubstrate 40 and are exfoliated by pulling exfoliation or high pressurefluid jet injection (please refer FIG. 32). Annealing for exfoliationcorresponds to (C).

After that, the UV tape 23 is exfoliated from the support substrate 40and the seed substrate 43 by UV irradiation hardening. Or it is possibleto separate the hydrogen ion implantation layer 44 by the laserprocessing exfoliation or the laser water jet processing exfoliationwithout the annealing for exfoliation.

After separating the seed substrate shown in FIG. 42(b), by C chamferingthe monocrystalline Si layer (hydrogen ion implantation) 44, thermaloxidation film SiO₂ 42 and the peripheral area of support substratesurface, lowering of cost is achieved by improving yield and qualitybecause the etching unevenness, the crack and the breaking of ultra slimSOI layer, etc. is reduced in the peripheral area. It is fine to dolight etching with hydrofluoric acid to remove the Si dust and the microcracks as required.

Meanwhile, the monocrystalline Si substrate of the seed substrate 42which is separated undergoes heat treatment, etc. under the conditionswhich include surface re-grinding, etching and hydrogen as required, andit becomes possible to reuse the monocrystalline Si substrate.

(5) Meantime, the surface of the exfoliated hydrogen ion implantationlayer (monocrystalline Si layer) 44 and a part of the surface of themonocrystalline Si layer 44 are etched with hydrofluoric acid enchant asrequired, and furthermore etched with the hydrogen anneal processing.The ultra slim SOI structure of the monocrystalline Si layer 44, forexample 1 μm, which has desired thickness and high even characteristics,is formed. The hydrogen annealing process can be done at 1050° C. for0.0013 nm/min and etching speed at 1100° C. for 0.0022 nm/min.

(6) The monocrystalline Si layer 44 is oxidized with heat and the SiO₂Layer 13 a with 100˜200 nm thickness is formed. The SiO₂ layer 13 a ofthe peripheral circuit area is removed by etching while leaving the SiO₂layer 13 a in the display area. The poly Si layer of 14 of 50˜100 nm isformed in the display area and the monocrystalline Si layer of 12 b of50˜100 nm is formed in the peripheral circuit area with Si epitaxialgrowth such as CVD (please refer FIG. 33). Each condition at this timecorresponds to (A).

At this time, the monocrystalline Si layer 44 is formed as a SiGe layerof the distortion impression semiconductor layer. If the SiGe layer ofthis distortion impression semiconductor layer is formed in the seed,with the distortion Si layer 12 b as the distortion channel layer withSi epitaxial growth such as CVD, the monocrystalline SiTFT peripheralcircuit can achieve a substantial improvement of approximately 1.76times electron mobility in comparison with the monocrystalline Si layer12 b of the former non-distortion channel layer.

In case of controlling the crystal grain size of the poly Si layer 14 inthe display area with solid phase deposition method, flash lampannealing method, laser annealing method or condensing lamp annealingmethod, etc. as required, the conditions correspond to (A).

At this time, the display area in the monocrystalline Si layer 44 withfilm thickness below the liquid crystal gap width is etched, the SiO₂Layer 13 a in the insulating layer is exposed, but is left in themonocrystalline Si layer 44 in the peripheral circuit the same as withFIG. 21(b) in (B). The poly Si layer 14 may be formed to 50˜100 nm onthe insulating layer of the display area with Si epitaxial growth suchas CVD and the monocrystalline Si layer 12 b may be formed to 50˜100 nmon the monocrystalline Si layer 44 on the peripheral circuit area.

At this time, the monocrystalline Si layer 44 as the SiGe layer of thedistortion impression semiconductor layer is formed. If the SiGe layerof this distortion impression semiconductor layer and the distortion Silayer 12 b as the distortion channel layer with Si epitaxial growth suchas CVD are formed, the monocrystalline SiTFT peripheral circuit can beformed which achieves the substantial improvement of approximately 1.76times the electron mobility in comparison with the monocrystalline Silayer 12 b of the former non-distortion channel layer.

And in case of controlling the crystal grain size of the poly Si layer14 in the display area with solid phase deposition method, flash lampannealing method, laser annealing method or condensing lamp annealingmethod, etc. as required, optionally, each conditions corresponds to(A).

Or, the same as with FIG. 21(c) in (B), the display area of themonocrystalline Si layer 44 with the film thickness which is below theliquid crystal gap width is etched as required and the SiO₂ layer 13 ain the insulating layer is exposed. The light-shielding metallic film 37of as transitional metallic silicide such as WSi₂(Tungsten silicide),TiSi₂(Titanium silicide), MoSi₂(Molybdenum silicide), is formed in thepoly SiTFT area of the pixel display inside the display area and coveredwith the insulating layer on top of it. The insulating layer of thesurface of the monocrystalline Si layer 444 in the peripheral circuitarea is removed.

The poly Si layer 14 is formed with thickness of 50˜100 nm on the SiO₂layer 13 a in the display area with Si epitaxial growth such as CVD andthe monocrystalline Si layer 12 b is formed with a thickness of 50˜100nm in the monocrystalline Si layer 44 on the peripheral circuit area.And in the case of controlling the crystal grain size of the poly Silayer 14 in the display area with solid phase deposition method, flashlamp annealing method, laser annealing method or condensing lampannealing method, etc. as required, the circumstances correspond to (A).

At this time, the monocrystalline Si layer 44 is formed as a SiGe layerof the distortion impression semiconductor layer. If the SiGe layer ofthis distortion impression semiconductor layer and the distortion Silayer 12 b are formed as distortion channel layer with Si epitaxialgrowth such as CVD, the monocrystalline SiTFT peripheral circuit canachieve the improvement, approximately 1.76 times the electron mobilityin comparison with the monocrystalline Si layer 12 b of the formernon-distortion channel layer.

The wiring, etc. is formed in the poly SiTFT area 15 a (please refer theFIG. 34 (a)) as the display element area of the poly Si layer 14 alongwith general purpose technology, the diode, resistance, the capacitor,coil and wiring, etc. of either the semiconductor device or thesemiconductor for integrated circuits in the monocrystalline SiTFT area15 b (please refer the FIG. 34 (a)) as the peripheral circuit area ofthe monocrystalline Si layer 12 b or both. The circumstance correspondsto (A).

In the mean time, because the monocrystalline Si layer 12 b has highelectron and positive hole mobility the same as the monocrystalline Sisubstrate, not only the peripheral drive circuit but also the imagesignal processing circuit, the picture quality compensation circuit, thememory circuit, CPU (Central Processing Unit) circuit, DSP (DigitalSignal Processor) circuit, etc. can be used. The circumstancecorresponds to (A).

The hydrogen ion implantation layer 45 is formed by filling with highdensity hydrogen ions to the depth of 3˜5 μm from the surface. Thedistortion layer 45 (please refer FIGS. 34(a) and (b)) is produced bythe anneal processing for exfoliation. The hydrogen ion implantation isdone at 300 Kev, 5×10¹⁶˜1×10¹⁷ atoms/cm² The annealing for exfoliationcorresponds to the aforementioned (4).

At this time, the hydrogen ion implantation layer 45 is formed afterprocessing at more than 500° C., to equalize the hydrogen ionimplantation layer 45 which has high density inside the monocrystallineSi substrate the same as mentioned above (C), and to prevent thehydrogen ion separation which has high density.

It is desirable to form this either after or before the exfoliationannealing after the hydrogen ion implantation. The electrode and wiring,etc. may become a cause of the hydrogen ion implantation depthdispersion.

However, in the case of the electrode and wiring formation before theexfoliation annealing, the exfoliation annealing with RTA of rapidheating rapid cooling from the back of the support substrate(monocrystalline Si substrate 40) is desirable with cooling for theultra slim TFT substrate layer side through the UV by the support jigwhich is liquid cooled.

At this time, although the Si device structure layer of SiO₂ layer 13 aand the poly Si layer 14, etc. exist on the support substrate 40, thehydrogen ion implantation layer 45 under the insulating layer 42 isformed by penetrating these and distortion layer 45 a is generated byheat treatment. The annealing for exfoliation is desirable with RTA ofrapid heating rapid cooling, however it is possible to generate thedistortion without having adverse effects to the device quality by doingfor example the Xe flash lamp annealing method for a very brief time(for example 700° C. for 10 millisecond).

Meantime, it is possible to separate the hydrogen ion implantation layer45 by laser processing exfoliation or laser water jet processingexfoliation without annealing for exfoliation, as cooling for the ultraslim TFT substrate layer side comes through the UV tape by the supportjig which is liquid cooled.

At this stage, it is desirable to form the groove 62 from themonocrystalline Si layer 12 b to at least the distortion area 45 a ofthe hydrogen ion implantation layer along with the divided line todivide the assembly into one panel of each ultra slim electroopticdisplay device unit afterwards, in other words along the dividedboundary line inside the scribe line. By forming the groove 62, it ispossible to separate easily from the support (Si) substrate 40, at thesame time, the process to divide will mentioned later because the ultraslim TFT substrate layer which will be mentioned later is dividedbeforehand inside the scribe line.

It is better to form the groove 62 at least to the distortion 41 a ofthe hydrogen ion implantation layer with dry etching (plasma etching andopposite spatter etching, etc. with such as SF₆, CF₄, Cl+O₂, HB r+O₂,etc.), wet etching (such as hydrofluoric acid etchant, alkaline etchantwith mixed liquid HF+H₂O₂+H₂O, mixed liquid HF+HNO₃+CH₃ COOH, etc.),mechanical processing (cutting groove by blade dicing, the diamondcutter, the cemented carbide cutter, the ultrasonic cutter etc.).

The poly Si layer 14 of the pixel opening section of the display area isremoved by etching (please refer FIG. 35). The circumstance correspondsto (A).

The 50˜200 nm thick transparent insulating layer (for example SiO₂ layer13 b, SiNx and SiO₂ laminating film, SiO₂ SiNx and SiO₂ laminating film,SiON, etc.) and the 100˜300 nm low reflection metallic film 17 are eachformed, the connection area (drain, source, gate, etc.) of the polySiTFT area 15 a on the poly Si layer 14 and the metallic film 17 on thebottom of the pixel opening section is etched, the transparent resin 16,etc. is filled in, and the surface is planarized with CMP, etc. Thecircumstance corresponds to (A).

(13) The transparent resin, etc. on the poly SITFT area 15 a drain ofthe display area is done with the window opening, the ultra slim TFTsubstrate layer is formed (please refer FIG. 36) by forming thetransparent electrode 18 a as the pixel electrode such as ITO, IZO, etc.The circumstance corresponds to (A). At the same time, the wiring insidethe peripheral circuit of the electrooptic display element substratelayer and the external output electrode (includes solder bump) areformed, but it is desirable to connect with the flexible substrate suchas an anisotropism conductive film connection, an ultrasonic connection,a solder bump, etc. and to mount to the PCB after forming the LCD panel.

The following process corresponds to (C).

In the meantime, in case of manufacturing the ultra slim reflective typeLCD, the ultra slim semi-transmissive type LCD, the ultra slim undersideluminous type organic EL and the ultra slim surface luminous typeorganic EL; the process (1)˜(4) (FIG. 31˜FIG. 34) is the same as for theultra slim transmissive type LCD, the process after that is the same as(A-2), (A-3), (A-4) and (A-5).

In the meantime, it has been explained with this execution figure,regarding the example using the hydrogen ion as an ion which fills to ahigh density, but it is not limited to this, but any ion which fills canbe used. It is possible to use the ions of an inert gas such as nitrogenor helium.

For example as for the hydrogen ion implantation is same as (C), thehydrogen negative ion beam implantation device which makes the plasmaincludes the hydrogen with the plasma production, which pulled out thehydrogen negative ion beam from this plasma, which fills this hydrogennegative ion to the specified depth, can be used other than the ionimplantation device (same as the ion implantation device which fillsimpurity such as former boron, phosphorus to the Si substrate) whichdoes the mass separation and scanning the hydrogen ion beam.

Like mentioned above, with the separation method for double ionimpanation in this execution figure, the SiO₂ layer 13 a is formed byheat oxidizing the monocrystalline Si layer 44 of the support substrate,the SiO₂ layer 13 a in the peripheral circuit area is removed whileleaving the SiO₂ layer 13 a in the display area. The poly Si layer 14 inthe display area and the monocrystalline Si layer 12 b in the peripheralcircuit area are each formed with Si epitaxial growth such as CVD.

Because the poly SITFT part 15 a as the display area in the poly Silayer 14 of the display area which has controlled crystal grain size(high electron and positive hole mobility) with such as flash lampannealing method or solid phase deposition method or laser annealingmethod or condensing lamp annealing method, etc., as required, eitherthe semiconductor device or the semiconductor for integrated circuits ofmonocrystalline SiTFT area 15 b, etc., as the peripheral circuit in themonocrystalline Si layer 12 b of the peripheral circuit area, or bothare formed. Because of this process, the poly SiTFT display elementwhich has arbitrarily controlled relatively low high electron andpositive hole mobility and low electric current leakage qualities, andthe monocrystalline SiTFT peripheral circuit which has high electron andpositive hole mobility and high drivability are formed inside the ultraslim TFT substrate layer on the same support substrate 40. With thisprocess, an ultra slim electrooptic display device unit which has highelectron and positive hole mobility and low electronic current leakagequalities, and which is high intensity, high definition andsophisticated can be obtained.

Or, with the separation method for another double ion implantation layerin this execution figure, the display area of the monocrystalline Silayer 44 of the support substrate 40 is etched, the insulating layer ofSiO₂ layer 42 is exposed, the poly Si layer 14 is formed in the displayarea with Si epitaxial growth such as CVD and the monocrystalline Silayer 12 b is formed in the peripheral circuit area. Because the polySiTFT part 15 a as the display area in the poly Si layer 14 of thedisplay area where arbitrarily controlled crystal grain size (highelectron and positive hole mobility) with such as flash lamp annealingmethod or solid phase deposition method or laser annealing method orcondensing lamp annealing method, etc., as required, either thesemiconductor device or the semiconductor for integrated circuits ofmonocrystalline SiTFT area 15 b, etc., is formed as the peripheralcircuit in the monocrystalline Si layer 12 b, or both. As a result ofthis process, the poly SiTFT display element which has arbitrarilycontrolled relatively low high electron and positive hole mobility andlow electric current leakage qualities, and the monocrystalline SiTFTperipheral circuit which has high electron and positive hole mobilityand high drivability, are formed inside the ultra slim TFT substratelayer on the same support substrate 40. With this process, an ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electronic current leakage qualities, and which ishigh intensity, high definition and sophisticated can be obtained.

Or, with the separation method for another double ion implantation layerin this execution figure, the display area of the monocrystalline Silayer 44 of the support substrate 40 is etched, the insulating layer ofSiO₂ layer 42 is exposed, the light shielding metallic layer is etchedwith CVD in the poly SiTFT forming area of the SiO₂ layer 42 of thedisplay area, the insulating layer is formed on top of this, the poly Silayer 14 is formed through the insulating layer in the display area withSi epitaxial growth such as CVD and the monocrystalline Si layer 12 b isformed in the peripheral circuit area. Because the poly SiTFT part 15 aas the display element part in the poly Si layer 14 of the display areawhere arbitrarily controlled crystal grain size (high electron andpositive hole mobility) with such as flash lamp annealing method orsolid phase deposition method or laser annealing method or condensinglamp annealing method, etc., as required, either the semiconductordevice or the semiconductor for integrated circuits of monocrystallineSiTFT area 15 b, etc., is formed as the peripheral circuit in themonocrystalline Si layer 12 b, or both. As a result of this process, thereflection of light of the is blocked by the light shielding metalliclayer, the poly SiTFT display element which has arbitrarily controlledrelatively low high electron and positive hole mobility and low electriccurrent leakage qualities, and the monocrystalline SiTFT peripheralcircuit which has high electron and positive hole mobility and highdrivability are formed inside the ultra slim TFT substrate layer on thesame support substrate 40. With this process, an ultra slim electroopticdisplay device unit which has high electron and positive hole mobilityand low electronic current leakage qualities, and which is highintensity, high definition and sophisticated can be obtained.

The poly Si layer 14 in the display area mentioned above contains aproper quantity (for example, a total of 10¹⁷˜10²² Atom/cc, preferably10¹⁸˜10²⁰ Atom/cc) in the formation film of a minimum of one kind ofgroup IV elements of Ge, Sn, Pb, etc. by ion implantation or ion dopingor CVD, etc. And by maintaining this condition, if we have a poly SiTFTdisplay element of the poly Si film which has re-crystallized thecrystal grain size with solid phase deposition method, flash lampannealing method, pulse condition or Continuous wave laser annealingmethod, condensing lamp annealing method, etc., for example theirregularity which exists in the crystal grain boundary of the poly Sifilm is decreased, and the film stress is decreased and it is easy toobtain the display part of the poly SiTFT with high carrier mobility andhigh quality.

And the poly SITFT display element, which has relatively low highelectron and positive hole mobility and low electric current leakagequalities, and the monocrystalline SiTFT peripheral circuit, which hashigh electron and positive hole mobility and high drivability, are bothformed inside the ultra slim TFT substrate layer on the same supportsubstrate 40. A high intensity, high definition and sophisticated ultraslim electrooptic display device unit which has high electron andpositive hole mobility and low electric current leakage qualities can beobtained.

Or, with the separation method for even another double ion impanationlayer in this execution layer, the monocrystalline Si layer 44 of thesupport substrate 40 is oxidized with heat and the SiO₂ layer 13 a isformed. The amorphous Si layer or the amorphous and the poly mixture Silayer or the poly Si layer are formed with plasma CVD, heat CVD,sputtering, evaporation, etc. The amorphous Si layer in the peripheralcircuit area or the amorphous and the poly mixture Si layer or the polySi layer and SiO₂ layer 13 a are etched and the monocrystalline Si film12 b is exposed. The amorphous SiTFT or the amorphous and the polymixture SiTFT or the poly SiTFT area 15 a is formed as the displayelement in the amorphous Si layer or the amorphous and the poly mixtureSi layer or the poly Si layer 14 of the display area, and either thesemiconductor element of the monocrystalline SiTFT part 15 b, etc. isformed in the peripheral circuit area in the monocrystalline Si layer 12b of the peripheral circuit area or the semiconductor integratingcircuit, or the both. Because of this process, the amorphous SiTFT orthe amorphous Si and the poly mixture SiTFT or the poly SiTFT displayelement which has arbitrarily controlled relatively low high electronand positive hole mobility and low electric current leakage qualities,and the monocrystalline SiTFT peripheral circuit which has high electronand positive hole mobility and high drivability are formed inside theultra slim TFT substrate layer on the same support substrate 40. Withthis process, an ultra slim electrooptic display device unit which hashigh electron and positive hole mobility and low electronic currentleakage qualities, and which is high intensity, high definition andsophisticated can be obtained.

Or, with the separation method for even another double ion impanationlayer in this execution layer, the display area of the monocrystallineSi layer 44 of the support substrate 40 is etched and the insulatinglayer of the SiO₂ layer 42 is exposed. The SiO₂ layer 13 a and theamorphous Si layer 14 of the insulating layer are formed with plasmaCVD, heat CVD, sputtering, evaporation, etc. The amorphous SiTFT or theamorphous Si and the poly mixture SiTFT or the poly SiTFT area 15 a asthe display element in the display area and the poly mixture Si layer orthe poly Si layer 14 of the display, and either the semiconductorelement of the monocrystalline SiTFT part 15 b, etc. as the peripheralcircuit area in the monocrystalline Si layer 12 b which the amorphous Silayer or the amorphous Si and the poly mixture Si layer or the poly Silayer 14 and the SiO₂ layer 13 a of the insulating layer is etched orthe semiconductor integrating circuit, or both are each formed. Becauseof this process, the amorphous SiTFT or the amorphous Si and the polymixture SiTFT or the poly SiTFT display element which has arbitrarilycontrolled relatively low high electron and positive hole mobility andlow electric current leakage qualities, and the monocrystalline SiTFTperipheral circuit which has high electron and positive hole mobilityand high drivability are formed inside the ultra slim TFT substratelayer on same support substrate 40. With this process, an ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electronic current leakage qualities, and which ishigh intensity, high definition and sophisticated can be obtained.

Or, with the separation method for even another double ion impanationlayer in this execution layer, the display area of the monocrystallineSi layer 44 of the support substrate 40 is etched and the insulatinglayer of the SiO₂ layer 42 is exposed. The light shielding metalliclayer 37 is formed by etching such as CVD in the display elementformation area of the SiO₂ layer 42 of the display area. The SiO₂ layer13 a and the amorphous Si layer 14 of the insulating layer are formedwith plasma CVD, heat CVD, sputtering, evaporation, etc. The amorphousSiTFT or the amorphous Si and the poly mixture SiTFT or the poly SiTFTarea 15 a as the display element in the display area and the polymixture Si layer or the poly Si layer 14 of the display, and either thesemiconductor element of the monocrystalline SITFT part 15 b, etc. isformed as the peripheral circuit area in the monocrystalline Si layer 12b which is the amorphous Si layer or the amorphous Si and the polymixture Si layer or the poly Si layer 14 and the SiO₂ layer 13 a of theinsulating layer are etched or the semiconductor integrating circuit, orboth. Because of this process, the reflected light form the back side isblocked with light shielding metallic layer 37, the amorphous SiTFT orthe amorphous Si and the poly mixture SiTFT or the poly SiTFT displayelement which has arbitrarily controlled relatively low high electronand positive hole mobility and low electric current leakage qualities,and the monocrystalline SiTFT peripheral circuit which has high electronand positive hole mobility and high drivability are formed inside theultra slim TFT substrate layer on the same support substrate 40. Withthis process, an ultra slim electrooptic display device unit which hashigh electron and positive hole mobility and low electronic currentleakage qualities, and which is high intensity, high definition andsophisticated can be obtained.

The amorphous Si layer or the amorphous and the poly mixture Si layer orthe poly Si layer 14 in the display area mentioned above contains theproper quantity (for example, a total of 10¹⁷˜10²² Atom/cc, preferably10¹⁸˜10²⁰ Atom/cc) in the formation film of a minimum of one kind ofgroup IV elements of Ge, Sn, Pb, etc. with ion implantation or iondoping or CVD, etc as required. And maintaining this condition, if wehave the poly SITFT display element of the poly Si film on which thecrystal grain size is re-crystallized the with solid phase depositionmethod, flash lamp annealing method, pulse condition or Continuous wavelaser annealing method, condensing lamp annealing method, etc., forexample, the irregularity which exists in the crystal grain boundary ofthe poly Si film is decreased, the film stress is decreased, and it iseasy to obtain the display part of the poly SiTFT with high carriermobility and high quality.

And the poly SiTFT display element which has relatively low highelectron and positive hole mobility and low electric current leakagequalities and the monocrystalline SiTFT peripheral circuit which hashigh electron and positive hole mobility and high drivability are formedinside the ultra slim TFT substrate layer on the same support substrate40. a high intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities can beobtained.

By the way, with the separation method for the double ion implantationlayer in this execution figure mentioned above, the SiGe layer 44 with aGe density of 20˜30% as the distortion impression semiconductor layer isformed through the insulating layer 42 on the support substrate 40, theSiO₂ layer 13 a is formed by heat oxidizing, the SiO₂ layer 13 a in theperipheral circuit area is removed while leaving the SiO₂ layer 13 a inthe display area, the poly Si layer 14 in the display area may be formedwith Si epitaxial growth such as CVD, the SiGe layer 44 of thedistortion impression semiconductor layer may be formed in theperipheral circuit area and the distortion Si layer 12 b as thedistortion channel layer in the seed.

And, the SiGe layer 44 with a Ge density of 20˜30% as the distortionimpression semiconductor layer is formed through the insulating layer 42on the support substrate 40, the SiGe layer 44 in the display area isetched and the SiO₂ layer 42 of the insulating layer is exposed, thepoly Si layer 14 in the display area may be formed with Si epitaxialgrowth such as CVD, the SiGe layer 44 of the distortion impressionsemiconductor layer may be formed in the peripheral circuit area and thedistortion Si layer 12 b as the distortion channel layer in the seed.

And, the SiGe layer 44 with a Ge density of 20˜30% as the distortionimpression semiconductor layer is formed through the insulating layer 42on the support substrate 40, the SiGe layer 44 in the display area isetched and the SiO₂ layer 42 of the insulating layer is exposed, theSiGe layer 44 in the display area is etched and the SiO₂ layer 42 in theinsulating layer is exposed, the poly Si layer 14 in the display areamay be formed with Si epitaxial growth such as CVD, the SiGe layer 44 ofthe distortion impression semiconductor layer may be formed in theperipheral circuit area and the distortion Si layer 12 b as thedistortion channel layer in the seed.

With this process, the monocrystalline SiTFT peripheral circuit whichachieves the substantial improvement of electron mobility ofapproximately 1.76 times in comparison with the monocrystalline Si layerof former non distortion channel layer, and which has high drivabilityis achieved, and the ultra slim electrooptic display device unit whichis high performance, high resolution, high function and high quality canbe obtained.

(E) The Separation Method for the Porous Semiconductor Layer and the IonImplantation Layer

Regarding this execution figure, I will explain about the manufacturingmethod of the ultra slim liquid crystal display device unit by theseparation method for the porous semiconductor layer and the ionimplantation layer (the semiconductor seed substrate is separated fromthe ion implantation layer which formed on the semiconductor seedsubstrate and the semiconductor support substrate is separated from theporous semiconductor layer which formed on the semiconductor supportsubstrate) which combined the porous semiconductor layer and the ionimplantation layer. From FIG. 37 to FIG. 39 are the manufacturingprocess figures for an ultra slim LCD with the separation method for theporous Si layer and the hydrogen ion implantation in the executionfigure of this invention.

(1) The hydrogen ion implantation layer 51 is formed by filling the highdensity hydrogen ion to the seed substrate 50, for example 12 inch Φ . .. with 1.2 mm thickness, which consists of the monocrystalline Si(please refer FIG. 37). In the mean time, the hydrogen ion can be filledwith the dose quantity of approximately 100 Kev, 5×10¹⁶˜×10¹⁷ atoms/cm²and approximately 1 μm depth (please refer the FIG. 31).

At this time, the same as with (D), the SiGe layer 51 with a Ge densityof 20˜30% as the distortion impression semiconductor layer is formed bythe Si epitaxial growth such as CVD on the surface of themonocrystalline Si substrate 50 to become a distortion impressionsemiconductor layer for the exfoliated hydrogen ion implantation layer51. The SiGe layer 51 may be formed with Si epitaxial growth after theseparation of the seed substrate, in the seed and the distortion Silayer of the distortion channel.

The aforementioned hydrogen ion is filled with high density beforehandto become this thickness (depth), and may make a hydrogen ionimplantation layer (SiGe layer) 51.

At this time, the Ge density of the surface of the SiGe layer 58 whichis a distortion impression semiconductor layer is set to become desireddensity by making the gradient structure where Ge density becomesdesired density at distortion layer of the hydrogen ion implantationlayer in the SiGe layer after separation of the seed substrate, it isdesirable to form the SiGe layer 58 which is a distortion impressionsemiconductor layer of this gradient structure to the seed substrate andthe distortion Si layer as a distortion channel layer with the Siepitaxial growth.

In other words, it is desirable to have the surface density of the SiGelayer 51 of the distortion impression semiconductor layer be at 20˜30%Ge density for example by increasing the Ge density gradually, aftergradient structure from the part connects to the insulating layer 57.

Or, it is fine for the monocrystalline Si substrate 50 itself to be themonocrystalline substrate which consists of SiGe of a Ge density of20˜30%.

(2) The low porous Si layer 53, the high porous Si layer 54 and the lowporous Si layer 55 are formed on the support substrate 52 which is forexample 12 inch Φ . . . and 1.2 mm thickness and which consists of themonocrystalline Si with the anode transformation method, themonocrystalline Si layer 56 is formed by semiconductor epitaxial growth,the insulating layer which consists of SiO₂ layer or SiO₂, Si₃N₄ andSiO₂ lamination film is formed (please refer FIG. 37). The formationmethod corresponds to (A).

(2) Attach the Seed Substrate 50 and the Support Substrate 52 (PleaseRefer FIG. 38).

Both of the surfaces of the hydrogen ion implantation 51 of the seedsubstrate 50 and the insulating layer 57 of the support substrate 52 arejoined at room temperature, and made them to connect with Van Del Waalspower. After this process, heat treatment for 30 minutes with 400° C.for covalent bonding makes the attachment stronger. It is necessary toset the heat processing at this time with a processing temperature and aprocessing time below the hydrogen ion separation temperature. The heatprocessing is same process explained as (B) except for the processingtemperature and the processing time.

Or, prior to this the, connecting surface is irradiated with an inertgas ion beam or an inert gas high-speed atomic beam such as argon in thevacuum at room temperature. The dust and soiling adhesion, etc. on thesurface is removed by sputter etching. By increasing the binding powerin order to connect to the surface and raising the optimal roughness canmake the bonding stronger.

(3) High density hydrogen which is filled by anneal processing forexfoliation is expanded by heat and the distortion is made to occur inthe hydrogen ion implantation layer 51 by pressure action and crystalre-arrangement action inside the micro bubbles, the UV tape 23 isattached on both the seed substrate 50 and the support substrate 52,then pulled to exfoliate them (please refer FIG. 39).

Although the annealing for exfoliation process corresponds to (C), it isimportant to adjust the porosity rate and the thickness of the porous Silayer 54 so as to not exfoliate from the high porous Si layer 54, atthis time.

Furthermore, it is possible to ease the porosity rate and thicknessconditions of the high porous Si layer 54 which is formed on the supportsubstrate, by injecting and exfoliating the high pressure fluid jet tothe hydrogen ion implantation layer 51 which is repeated as required, orby exfoliating with laser processing or laser water jet processing thehydrogen ion implantation layer 51 which does not anneal forexfoliation.

The peripheral area of the surface of the monocrystalline Si layer(hydrogen ion implantation layer), the insulating layer 57, themonocrystalline Si layer 56, the low porous Si layer 55, the high porousSi layer 54, the low porous Si layer 53 and the support substrate 52 areC-chamfered. This prevents etching unevenness, cracking and breaking ofthe ultra slim SOI layer of the peripheral area, and a cost decrease isachieved by improving the yield and quality. The light etching may bedone by the hydrofluoric acid etchant to remove the Si dust and microcracks as required.

The high density hydrogen, which is filled with ions by local heating ofthe laser processing exfoliation method, is expanded by heat as thefacing substrate side 21 is cooled through the UV tape and the supportjig which is liquid cooled as required. The support substrate(monocrystalline Si substrate) 52 is separated by creating thedistortion layer 51 in the hydrogen ion implantation layer 51 bypressure action of the micro bubbles and crystal re-arrangement action.

In the meantime, the support jig which is cooled with liquid is notalways necessary because of the cooling action of the water that isirradiated with the laser for the exfoliation method of laser water jetprocessing.

(5) A part of the surface of the monocrystalline Si layer 58 which isexfoliated by the hydrofluoric acid etchant as required, furthermore itis etched with etchant by the hydrogen annealing process and themonocrystalline Si layer 58 is formed with desired thickness and evencharacteristics, for example 1 μm.

The etching speed of the hydrogen annealing is done with 1050° C. for0.0013 nm/min, 1100° C. for 0.0022 nm/min.

The process listed hereafter this corresponds to (B).

The SiO₂ layer 13 a is formed by heat oxidizing the monocrystalline Silayer 58, and the SiO₂ layer 13 a of the peripheral circuit area isremoved by etching while leaving the SiO₂ layer 13 a of the displayarea. The poly Si layer 14 is formed with 50˜100 nm in the display areawith Si epitaxial growth of the CVD method and the monocrystalline Silayer 12 b is formed with 50˜100 nm in the peripheral circuit area.

At this time, in the case of forming the SiGe layer 51 with the a Gedensity of 20˜30% by the Si epitaxial growth such as CVD on the surfaceof the monocrystalline Si substrate 50 to become the distortionimpression semiconductor layer for the hydrogen ion implantation layer(monocrystalline Si layer) 58 which is exfoliated as mentioned in (D),the SiGe layer 58 as the distortion impression semiconductor layer inthe seed and the distortion Si layer 12 b with Si epitaxial growth maybe completed with a laminated layer.

With this process, because the peripheral circuit of MOSTFT achieves thesubstantial improvement of electron mobility of approximately 1.76 timesin comparison with the monocrystalline Si layer of former non distortionchannel layer, and which has high drivability is achieved, and the ultraslim electrooptic display device unit which is high performance, highresolution, high function and high quality can be obtained.

And in case of arbitrarily controlling the crystal grain size (highelectron and positive hole mobility) of the poly Si layer 14 in thedisplay area with solid phase deposition method, flash lamp annealingmethod, laser annealing method or condensing lamp annealing method,etc., each circumstance corresponds to (A).

Or, the display area of the monocrystalline Si layer 58 whose filmthickness is below the liquid crystal gap width is etched, and theinsulating layer is exposed. The poly Si layer with 50˜100 nm may beformed on the insulating layer of the display area with semiconductorepitaxial growth of CVD method and the monocrystalline Si layer 12 b maybe formed in the monocrystalline Si layer 58 with 50˜100 nm on theperipheral circuit area while leaving the monocrystalline Si layer 58 inthe peripheral circuit area.

And in case of arbitrarily controlling the crystal grain size (highelectron and positive hole mobility) of the poly Si layer 14 in thedisplay area with flash lamp annealing method, solid phase depositionmethod, laser annealing method or condensing lamp annealing method,etc., each circumstance corresponds to (A).

Or, the light-shielding metallic film 37 is formed under the TFT area ofthe poly Si layer 14 in the display area as required, and in case ofarbitrarily controlling the crystal grain size (high electron andpositive hole mobility) of the poly Si layer 14 in the display area withflash lamp annealing method, solid phase deposition method, laserannealing method or condensing lamp annealing method, etc., eachcircumstance corresponds to (A).

At this time, the display area of the monocrystalline Si layer 58 whosefilm thickness is below the liquid crystal gap width is etched and theinsulating layer 57 is exposed. The light shielding metallic layer 37such as transitional metallic silicide such as WSi₂(Tungsten silicide),TiSi₂(Titanium silicide), MoSi₂(Molybdenum silicide) etc., is formed ontop of it in the poly SiTFT area for pixel display inside the displayarea and it is covered with the insulating layer. The insulating layerof the surface of the monocrystalline Si layer 58 in the peripheralcircuit area is removed.

The poly Si layer 14 which is 50˜100 nm thickness may be formed on theinsulating layer of the display area with semiconductor epitaxial growthof the CVD method and the monocrystalline Si layer 12 b which is 50˜100nm thickness may be formed in the monocrystalline Si layer 58 on theperipheral circuit area.

Furthermore, although the external output electrode such as the solderbump which connects the peripheral circuit in the ultra slim TFTsubstrate layer is formed, it is desirable to connect the flexiblesubstrate with such as an anisotropic electric conduction filmconnection, ultrasonic connecting, solder attachment, etc. and to mountto the PCB after forming the LCD panel.

In this way, the poly Si layer or the amorphous Si layer of the pixelopening section in the display area of the ultra slim TFT substratelayer on this support substrate is removed and filled with a opticallytransparent material and the surface planarized, the pixel electrodewhich connects to the pixel display element is formed on top of it.After laminating and sealing the ultra slim TFT substrate layer (ultraslim SOI layer) and the facing substrate on the support substrate, thesupport substrate is separated form the porous Si layer. The porous Silayer, etc. which is left after the exfoliation is etched as required,the optically transparent material of the surface which is separated isexposed and attached to the transparent support substrate withtransparent sealant. With this process, an ultra slim transmissive typeLCD which has high electron and positive hole mobility and low electriccurrent leakage qualities, and which is high intensity, high definitionand sophisticated can be obtained.

In the meantime, in case of manufacturing the ultra slim reflective typeLCD, the ultra slim semi-transmissive type LCD, the ultra slim undersideluminous type organic EL and the ultra slim surface luminous typeorganic EL, the process concerning (1)˜(4) (FIG. 37˜FIG. 39) is the sameas the ultra slim transmissive type LCD, the process from that point isthe same as (A-2), (A-3), (A-4) and (A-5).

In the meantime, this execution figure has explanation which shows anexample which uses the hydrogen ion as the ion which is filled to highdensity, but the ion which is used to fill is not limited to hydrogen.It is possible to use ions from inert gases such as nitrogen and helium.

For example as for hydrogen ion implantation is same as (C), thehydrogen negative ion beam implantation device which makes the plasmaincludes the hydrogen with the expedient plasma production, which pullsout the negative hydrogen ion beam from this plasma, which fills thishydrogen negative ion to the specified depth, can be used other than theion implantation device (the same as the ion implantation device whichfills impurity such as former boron, phosphorus to the Si substrate)which does the mass separation and scanning of the hydrogen ion beam.

In other words, with the separation method for the porous Si layer andthe hydrogen ion implantation layer in this execution figure, the SiO₂layer is formed by heat oxidizing the monocrystalline Si layer 58 on thesupport substrate 52 after its separation, the SiO₂ layer in theperipheral circuit area is removed while leaving the SiO₂ layer in thedisplay area. The poly Si layer 14 in the display area and themonocrystalline Si layer 12 b in the peripheral circuit area are eachformed with Si epitaxial growth such as CVD.

Because the display area of the poly SiTFT part 14 in the display areawhere the crystal grain size (high electron and positive hole mobility)is arbitrarily controlled and the peripheral circuit area of themonocrystalline Si layer 12 b in the peripheral circuit area are eachformed with a method such as flash lamp annealing method or solid phasedeposition method or laser annealing method or condensing lamp annealingmethod, etc., as required, the poly SiTFT display element which hasrelatively low high electron and positive hole mobility which isarbitrarily controlled, and which has low electric current leakagequalities, and the monocrystalline SiTFT peripheral circuit which hashigh electron and positive hole mobility and high drivability are formedinside the ultra slim TFT substrate layer of the ultra slim SOI layer onthe same support substrate 52. With this process, an ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electronic current leakage qualities, and which ishigh intensity, high definition and sophisticated can be obtained.

Or, with the separation method for another porous Si layer and hydrogenion impanation in this execution figure, the display area of themonocrystalline Si layer 58 of the support substrate 52 after is etchedits separation and the insulating layer 57 is exposed while leaving theperipheral circuit area. The poly Si layer 14 in the display area andthe monocrystalline Si layer 12 b in the peripheral circuit area areeach formed with Si epitaxial growth such as CVD.

Because the display area in the poly SiTFT part 14 of the display areawhere the crystal grain size (high electron and positive hole mobility)is arbitrarily controlled and the peripheral circuit area of themonocrystalline Si layer 12 b in the peripheral circuit area are eachformed with a method such as flash lamp annealing method or solid phasedeposition method or laser annealing method or condensing lamp annealingmethod, etc., as required, the poly SiTFT display element which hasrelatively low high electron and positive hole mobility which isarbitrarily controlled, and which has low electric current leakagequalities, and the monocrystalline SiTFT peripheral circuit which hashigh electron and positive hole mobility and high drivability are formedinside the ultra slim TFT substrate layer of the ultra slim SOI layer onthe same support substrate 52. With this process, an ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electronic current leakage qualities, and which ishigh intensity, high definition and sophisticated can be obtained.

Or, with the separation method for yet another porous Si layer and thehydrogen ion implantation in this execution figure, the display area ofthe monocrystalline Si layer 58 of the support substrate 52 is etchedafter its separation and the insulating layer 57 is exposed. The lightshielding metallic layer 37 such as transitional metallic silicide inthe poly SiTFT area for the pixel display inside the display area isformed and the top of it is covered with the insulating. Then, theinsulating layer of the surface of the monocrystalline Si layer 58 inthe peripheral circuit area is removed. The poly Si layer 14 on theinsulating layer in the display area and the monocrystalline Si layer 12b in the peripheral circuit area are each formed with Si epitaxialgrowth such as CVD. Because the display area in the poly SiTFT part 14of the display area where the crystal grain size (high electron andpositive hole mobility) is arbitrarily controlled and the peripheralcircuit area of the monocrystalline Si layer 12 b in the peripheralcircuit area are each formed with a method such as flash lamp annealingmethod or solid phase deposition method or laser annealing method orcondensing lamp annealing method, etc., as required, the poly SiTFTdisplay element which has relatively low high electron and positive holemobility which is arbitrarily controlled, and which has low electriccurrent leakage qualities, and the monocrystalline SiTFT peripheralcircuit which has high electron and positive hole mobility and highdrivability are formed inside the ultra slim TFT substrate layer of theultra slim SOI layer on the same support substrate 52. With thisprocess, an ultra slim electrooptic display device unit which has highelectron and positive hole mobility and low electronic current leakagequalities, and which is high intensity, high definition andsophisticated can be obtained.

And, with the separation method for the porous Si layer and the hydrogenion implantation layer in this execution figure, the monocrystalline Silayer 58 on the support substrate after its separation is formed on theSiO₂ layer with heat oxidizing, for example, the amorphous Si layer orthe amorphous and the poly mixture Si layer or the poly Si layer 14 areformed extensively with plasma CVD, heat CVD, sputtering, evaporation,etc. The amorphous Si layer or the amorphous and the poly mixture Silayer or the poly Si layer 14 and the SiO₂ layer in the peripheral areaare etched and the monocrystalline Si layer 58 is exposed. Because theamorphous SiTFT or the amorphous and the poly mixture SiTFT or the polySiTFT area is formed as the display element part in the amorphous Silayer or the amorphous and the poly mixture Si layer or the poly Silayer 14 of the display area, either the semiconductor device or thesemiconductor for integrated circuits of monocrystalline SiTFT area,etc., is formed as the peripheral circuit in the monocrystalline Silayer 58 of the peripheral circuit area, or both. Because of thisprocess, the amorphous SiTFT or the amorphous and the poly mixture SiTFTor the poly SiTFT display element which has arbitrarily controlledrelatively low high electron and positive hole mobility and low electriccurrent leakage qualities, and the monocrystalline SiTFT peripheralcircuit which has high electron and positive hole mobility and highdrivability are formed inside the ultra slim TFT substrate layer of theultra slim SOI layer on the same support substrate. With this process,an ultra slim electrooptic display device unit which has high electronand positive hole mobility and low electronic current leakage qualities,and which is high intensity, high definition and sophisticated can beobtained.

Or, with the separation method for another porous Si layer and thehydrogen ion implantation layer in this execution figure, the displayarea of the monocrystalline Si layer 58 of the support substrate isetched after its separation and the insulating layer is exposed. Theinsulating layer of the SiO₂ layer and the amorphous Si layer or theamorphous and the poly mixture Si layer or the poly Si layer 14 areformed extensively with plasma CVD, heat CVD, sputtering, evaporation,etc. The amorphous Si layer or the amorphous and the poly mixture Silayer or the poly Si layer 14 and the SiO₂ layer in the peripheral areaare etched and the monocrystalline Si layer 58 is exposed. Because theamorphous SiTFT or the amorphous and the poly mixture SiTFT or the polySiTFT area as the display element part is formed in the amorphous Silayer or the amorphous and the poly mixture Si layer or the poly Silayer 14 of the display area, either the semiconductor device or thesemiconductor for integrated circuits of monocrystalline SiTFT area,etc., is formed as the peripheral circuit in the monocrystalline Silayer 58 of the peripheral circuit area, or both. Because of thisprocess, the amorphous SiTFT or the amorphous and the poly mixture SiTFTor the poly SiTFT display element which has arbitrarily controlledrelatively low high electron and positive hole mobility and low electriccurrent leakage qualities, and the monocrystalline SiTFT peripheralcircuit which has high electron and positive hole mobility and highdrivability are formed inside the ultra slim TFT substrate layer of theultra slim SOI layer on the same support substrate. With this process,an ultra slim electrooptic display device unit which has high electronand positive hole mobility and low electronic current leakage qualities,and which is high intensity, high definition and sophisticated can beobtained.

Or, with the separation method for yet another porous Si layer and thehydrogen ion implantation layer in this execution figure, the displayarea of the monocrystalline Si layer 58 of the support substrate isetched after its separation and the insulating layer 57 is exposed. Thelight shielding metallic layer is formed by etching and CVD in the pixeldisplay element formation area on the insulating layer of the displayarea. The insulating layer of the SiO₂ layer and the amorphous Si layeror the amorphous and the poly mixture Si layer or the poly Si layer 14are formed extensively with plasma CVD, heat CVD, sputtering,evaporation, etc. The amorphous Si layer or the amorphous and the polymixture Si layer or the poly Si layer 14 and the SiO₂ layer in theperipheral area are etched and the monocrystalline Si layer 58 isexposed. Because the amorphous SiTFT or the amorphous and the polymixture SITFT or the poly SITFT area is formed as the display elementarea in the amorphous Si layer or the amorphous and the poly mixture Silayer or the poly Si layer 14 of the display area either thesemiconductor element or the semiconductor for integrated circuits ofmonocrystalline SiTFT area, etc., is formed as the peripheral circuit inthe monocrystalline Si layer 58 of the peripheral circuit area, or bothare. Because of this process, the amorphous SiTFT or the amorphous andthe poly mixture SiTFT or the poly SiTFT display element whose reflectedlight on the back is blocked by the metallic layer for shielding, whichhas arbitrarily controlled relatively low high electron and positivehole mobility and low electric current leakage qualities, and themonocrystalline SiTFT peripheral circuit which has high electron andpositive hole mobility and high drivability are formed inside the ultraslim TFT substrate layer of the ultra slim SOI layer on the same supportsubstrate. With this process, an ultra slim electrooptic display deviceunit which has high electron and positive hole mobility and lowelectronic current leakage qualities, and which is high intensity, highdefinition and sophisticated can be obtained.

The amorphous Si layer or the amorphous and the poly mixture Si layer orthe poly Si layer 14 mentioned above contains the proper quantity (forexample, a total of 10¹⁷˜10²² atom/cc, preferably 10¹⁸˜10²⁰ atom/cc) inthe formation film of a minimum of one kind of group IV elements of Ge,Sn, Pb, etc. as required, with ion implantation or ion doping or CVD,etc. After this, if we have the poly SiTFT display element of the polySi film which is re-crystallized selectively for crystal grain size withsolid phase deposition method, flash lamp annealing method, pulsecondition or Continuous wave laser annealing method, condensing lampannealing method, etc., for example, the irregularity which exists inthe crystal grain boundary of the poly Si film is decreased, and thefilm stress is decreased, it is easy to obtain the display area of thepoly SiTFT with high carrier mobility and high quality.

And the poly SiTFT display element which has relatively low highelectron and positive hole mobility and low electric current leakagequalities and the monocrystalline SiTFT peripheral circuit which hashigh electron and positive hole mobility and high drivability are formedinside the ultra slim TFT substrate layer on the same support substrate40. A high intensity, high definition and sophisticated ultra slimelectrooptic display device unit which has high electron and positivehole mobility and low electric current leakage qualities can be easy toobtain.

By the way, with the separation method for the porous layer and the ionimplantation layer in this execution figure mentioned above, the SiGelayer 51 (hydrogen ion implantation layer) with a Ge density of 20˜30%as the distortion impression semiconductor layer on the surface of theseed substrate 50 is formed on the support substrate 40, the SiO₂ layer13 a is formed by heat oxidizing the monocrystalline Si layer 58(distortion impression semiconductor layer of the SiGe layer) on thesupport substrate after the seed substrate separation, the SiO₂ layer 13a in the peripheral circuit area is removed while leaving the SiO₂ layer13 a in the display area, the poly Si layer 14 in the display area maybe formed with Si epitaxial growth such as CVD, the SiGe layer 58 of thedistortion impression semiconductor layer may be formed in theperipheral circuit area and the distortion Si layer 12 b may be formedas the distortion channel layer in the seed.

Or, the SiGe layer 51 (hydrogen ion implantation layer) with a Gedensity of 20˜30% as the distortion impression semiconductor layer onthe surface of the seed substrate 50 is formed, the display area of themonocrystalline Si layer 58 (distortion impression semiconductor layerof the SiGe layer) on the support substrate is etched after the seedsubstrate separation and the SiO₂ layer 42 of insulating layer isexposed, the poly Si layer 14 may be formed in the display area with Siepitaxial growth such as CVD, the SiGe layer 58 of the distortionimpression semiconductor layer may be formed in the peripheral circuitarea and the distortion Si layer 12 b may be formed as the distortionchannel layer in the seed.

Furthermore, the SiGe layer 51 (hydrogen ion implantation layer) withthe a Ge density of 20˜30% is formed as the distortion impressionsemiconductor layer on the surface of the seed substrate 50, the displayarea of the monocrystalline Si layer 58 (distortion impressionsemiconductor layer of the SiGe layer) on the support substrate isetched after the seed substrate separation, the SiO₂ layer 42 of theinsulating layer is exposed, the light shielding metallic layer isformed on the display element formation area, the insulating layer isformed on top of that, the poly Si layer 14 may be formed in the displayarea with Si epitaxial growth such as CVD, the SiGe layer 58 of thedistortion impression semiconductor layer may be formed in theperipheral circuit area and the distortion Si layer 12 b may be formedas the distortion channel layer in the seed may be formed.

Because of this, the monocrystalline SiTFT peripheral circuit of thedistortion channel layer whose drivability is high and which achievedthe improvement of substantial electron mobility of approximately 1.76times in comparison with the monocrystalline Si layer of former nondistortion channel layer is achieved, the ultra slim electroopticdisplay device unit which has high function, high resolution and highquality can be obtained.

On (A)˜(E), (F) mentioned above, although I have explained mainlyconcerning the example of processes that are generally known such as thedouble surface assembly which is done with the condition of laminatingeach substrate with the other substrate (surface), it is possible to dothis using the generally known process of surface single assembly whichis done by laminating these substrates as a preliminary chip condition(single). Below, I will explain each of the common methods of assemblyfor each of the reflective type LCD, the transmissive type LCD, thesemi-transmissive type LCD, the surface luminous type organic EL and theunderside luminous type organic EL types are formed from electroopticdisplay element substrate with each method (A)˜(E) mentioned above.

(Reflective Type LCD)

With (A)˜(E) mentioned above, the display part of the poly SiTFT or theamorphous SiTFT and the peripheral circuit of the monocrystalline SiTFTare formed, the ultra slim electrooptic display element substrate layerwhich has completes the alignment layer formation and alignment process,and the facing substrate which has completed the alignment layerformation and alignment process through the transparent electrodeformation are sealed by laminating through the specified liquid crystalgap. The support substrate is separated from the separation layer suchas the distortion area of the porous layer or the ion implantationlayer, and then the ultra slim electrooptic display element substrate isformed. After that, it is attached to the backing with the sealant, andeach ultra slim electrooptic display device unit is injected with liquidcrystal after cutting and dividing. Or, the non-deformative chip of thebacking is attached with the sealant together with the non-deformativechip inside the ultra slim electrooptic display element substrate afterits separation, and the liquid crystal is injected after cutting anddividing.

At this time, after injecting the liquid crystal and laminating andsealing together, the support substrate may be separated from theseparation layer at such as the distortion area of the porous layer orthe ion implantation layer.

Or, with (A)˜(E) mentioned above, the display part of the poly SiTFT orthe amorphous SiTFT and the ultra slim electrooptic display elementsubstrate element of the peripheral circuit part of the monocrystallineSiTFT are formed, the surface is protected by the UV tape, theelectrooptic display element substrate is formed by attaching thebacking with the sealant after separating the support substrate from theseparation layer. After that, in the case of the surface assemblysystem, this electrooptic display element substrate that has completedthe alignment layer forming and alignment process, the facing substratewhich is formed with the transparent electrode and which has completedthe alignment layer forming and alignment process, are sealed bylaminating the specified liquid crystal gap, then the liquid crystal isinjected after cutting and dividing.

Or, in case of the surface single assembly system, the non-deformativechip of the facing substrate which is formed with the transparentelectrode which has completed the alignment layer forming and alignmentprocess and then been cut, and the non-deformative chip inside the ultraslim electrooptic display element substrate which has completed thealignment layer forming and alignment process, are sealed by laminatingwith the specified liquid crystal gap. After injecting the liquidcrystal, the support substrate is separated from the separation layer,and the electrooptic display element substrate is formed by attachingthe backing with the sealant after separating the support substrate fromthe separation layer.

(Transmissive Type LCD)

With (A)˜(E) mentioned above, after the display area of the poly SiTFTor the amorphous SiTFT and the ultra slim electrooptic display elementsubstrate layer of the peripheral circuit of the monocrystalline SiTFTare formed, the pixel opening section of the display area is etched andplanarized with the transparent material. The transparent electrodewhich is connected to the drain of the TFT is formed there it hascompleted the alignment layer forming and alignment process. Aftersealing with the facing substrate, which has completed the alignmentfilm forming, which forms the transparent electrode, and alignmentprocess, by laminating at the specified liquid crystal gap, the supportsubstrate is separated from the separation layer and the ultra slimelectrooptic display element substrate is formed. The transparentbacking is attached with the transparent sealant and it is injected withthe liquid crystal after cutting and dividing. Or the non-deformativechip inside the ultra slim electrooptic display element substrate isattached after the separation to the non-deformative chip of thetransparent backing with the transparent sealant and it is injected withliquid crystal after cutting and dividing.

Or, with (A)˜(E) mentioned above, the display area of the poly SITFT orthe amorphous SiTFT and the ultra slim electrooptic display elementsubstrate element of the peripheral circuit section of themonocrystalline SiTFT are formed, the surface is protected by UV tape,the support substrate is separated from the separation layer, the ultraslim electrooptic display element substrate is formed, the electroopticdisplay element substrate is formed by attaching the backing with thesealant. After that, in the case of the surface assembly system, thepixel opening section of the display area of this electrooptic displayelement substrate is etched and its surface is planarized with thetransparent material. After forming the transparent electrode whichconnects to the drain of TFT, and the alignment layer formation andalignment process has completed, the facing substrate which is formedwith the transparent electrode and which has completed the alignmentlayer formation and alignment process, is sealed by laminating with thespecified liquid crystal gap, then the liquid crystal is injected afterthe cutting and dividing.

Or, in case of the single face assembly system, the non-deformative chipof the facing substrate which has completed the alignment filmformation, the alignment process and has been cut after forming thetransparent electrode, the pixel opening section of the display area isetched and then it is embedded and planarized with the transparentmaterial, after forming the transparent electrode which connects to thedrain of the TFT, it is sealed with the non-deformative chip inside theelectrooptic display element substrate which has completed the alignmentfilm formation and alignment process to the specified liquid crystalgap, the liquid crystal is injected then it is cut and divided.

Furthermore, the non-deformative chip of the facing substrate which hascompleted the alignment film formation, alignment process and been cutafter forming the transparent electrode, the pixel opening section ofthe display area is etched and then it is embedded and planarized withthe transparent material, the transparent electrode which connects tothe drain of the TFT is formed, then it is sealed with thenon-deformative chip of the electrooptic display element substrate whichhas completed the alignment film formation and alignment process andbeen cut, at the specified liquid crystal gap, it is injected withliquid crystal.

(Semi-Transmissive LCD)

Or, with (A)˜(E) mentioned above, after the display area of the polySITFT or the amorphous SiTFT and the ultra slim electrooptic displayelement substrate layer of the peripheral circuit of the monocrystallineSiTFT are formed, the pixel opening section of the display area isetched and it is embedded and planarized with the transparent material.The reflective electrode which connects to the drain of TFT and thetransparent electrode are formed there, and it completes the alignmentfilm formation and alignment process. After sealing by laminating withthe specified liquid crystal gap with the facing substrate which isformed with a transparent electrode and which has completed thealignment film formation and alignment process, the support substrate isseparated from the separation layer, and the ultra slim electroopticdisplay element substrate is formed. After attaching the transparentbacking with the transparent sealant, it is injected with liquid crystalafter cutting and dividing. Or the non-deformative chip inside theelectrooptic display element substrate is attached after the separationto the transparent backing with the transparent sealant, and then it isinjected with the liquid crystal after cutting and dividing.

Or, with (A)˜(E) mentioned above, the display area of the poly SiTFT orthe amorphous SiTFT and the ultra slim electrooptic display elementsubstrate element of the peripheral circuit of the monocrystalline SiTFTsection are formed, the surface is protected by the UV tape, the supportsubstrate is separated from the separation layer, the ultra slimelectrooptic display element substrate is formed, the electroopticdisplay element substrate is formed by attaching the backing with thesealant. After that, in case of the face assembly system, the pixelopening section of the display area of this electrooptic display elementsubstrate is etched and it is embedded and planarized with thetransparent material. After forming the reflection and the transparentelectrode which connect to the drain of TFT, it has completed thealignment film formation and alignment process. The facing substratewhich has completed the alignment film formation and alignment process,is sealed with the specified liquid crystal gap by laminating, it isinjected with liquid crystal after cutting and dividing.

Or, in case of the single face assembly system, the non-deformative chipof the facing substrate which has completed the alignment filmformation, alignment process and been cut after forming the transparentelectrode, the pixel opening section of the display area is etched andthen it is embedded and planarized with the transparent material, afterforming the reflection and the transparent electrode which connect tothe drain of the TFT there, it is sealed with the non-deformative chipinside the electrooptic display element substrate which has completedthe alignment film formation and alignment process to the specifiedliquid crystal gap, it is injected with liquid crystal then it is cutand divided.

Furthermore, the non-deformative chip of the facing substrate which hascompleted the alignment film formation, alignment process and cut afterforming the transparent electrode, the pixel opening section of thedisplay area is etched and then it is embedded and planarized with thetransparent material, the reflection and the transparent electrode whichconnect to the drain of the TFT there is formed, then it is sealed withthe non-deformative chip of the electrooptic display element substratewhich has completed the alignment film formation and alignment processand cut, to the specified liquid crystal gap, it is injected with liquidcrystal.

(Surface Emitter Type Organic EL)

With (A)˜(E) mentioned above, the display area of the poly SiTFT or theamorphous SiTFT and the ultra slim electrooptic display elementsubstrate layer of the peripheral circuit of the monocrystalline SiTFTare formed. Here, the display area is attached to the organic ELemission layer such as red, blue and green to every pixel on the cathode(Li-AL, Mg—Ag, etc.) which is connected to the drain of the MOSTFT fordrive current for each pixel, the anode (the ITO film, etc.) is formedon the top of the area, the anode is formed extensively as required, thestructure, which is covered with the moisture proof transparent resin,is formed on the whole surface. And the support substrate is separatedfrom the separation layer, the ultra slim electrooptic display elementsubstrate is formed. After that, the support substrate is attached tothis ultra slim electrooptic display element substrate with the sealant,and then it is cuts and divided. Or the non-deformative chip inside theultra slim electrooptic display element substrate is attached to thenon-deformative chip of the support substrate with the sealant, and itis cut and divided.

Or, with (A)˜(E) mentioned above, the display section of the poly SiTFTor the amorphous SiTFT and the ultra slim electrooptic display elementsubstrate element of the peripheral circuit of the monocrystalline SiTFTare formed, the surface is protected by the UV tape, the supportsubstrate is separated from the separation layer, the ultra slimelectrooptic display element substrate is formed, the electroopticdisplay element substrate is formed by attaching the backing with thesealant.

Here, the display section is deposited on the organic EL emission layersuch as red, blue and green to every pixel on the cathode (Li-AL, Mg—Ag,etc.) which is connected to the drain of the MOSTFT for drive current toeach pixel, the anode (the ITO film, etc.) is formed on the top of thesection, the anode is formed extensively as required, the structurewhich is covered with the moisture proof transparent resin is formed onthe whole surface. After that, it is cut and divided.

With (A)˜(E) mentioned above, after forming the display section of thepoly SiTFT or the amorphous SiTFT and the ultra slim electroopticdisplay element substrate layer of the peripheral circuit of themonocrystalline SiTFT is formed, the pixel opening section of thedisplay section is etched and it is embedded and planarized with thetransparent material. The anode (ITO film, etc.) which is connected tothe source of MOSTFT for electronic driving of each pixel are formed ontop of it. Furthermore, the organic EL emission layer such as red, blueand green in each pixel is deposited, the cathode (Li-AL, Mg—Ag) isformed on the top section, the cathode is formed extensively asrequired, furthermore the structure which is covered with the moistureproof transparent resin is formed. And the support substrate isseparated from the separation layer, and the ultra slim electroopticdisplay element substrate is formed. After that, the transparent supportsubstrate is attached with the transparent sealant and it is cut anddivided.

Or the non-deformative chip inside the electrooptic display elementsubstrate and the non-deformative chip of the transparent backing areattached with the transparent sealant and it is cut and divided.

Or, with (A)˜(E) mentioned above, the display section of the poly SiTFTor the amorphous SiTFT and the ultra slim electrooptic display elementsubstrate element of the peripheral circuit of the monocrystalline SiTFTare formed, the surface is protected by the UV tape, the supportsubstrate is separated from the separation layer, the ultra slimelectrooptic display element substrate is formed, and the electroopticdisplay element substrate is formed by attaching the transparent backingwith the transparent sealant.

The pixel opening section of the display part of this electroopticdisplay element substrate is etched, and it is embedded and planarizedwith the transparent material. The anode which is connected to thesource of TFT for electronic driving in each pixel is formed on top ofit, furthermore the organic EL emission layer such as red, blue andgreen in every pixel is deposited on top of the area, the cathode isformed extensively as required, furthermore, the structure which iscovered with the moisture proof transparent resin is formed on the wholesurface. After that, it is cut and divided.

The assembly method mentioned above (A)˜(E) is shown from FIG. 48 toFIG. 52, classifying by the method of separation. FIG. 48 shows an LCDwith the separation method for the porous semiconductor layer of (A) andthe assembly method of organic EL, FIG. 49 shows an LCD with theseparation method for the double porous semiconductor layer of (B) andthe assembly method of organic EL, FIG. 50 shows an LCD with theseparation method for the ion implantation layer of (C) and the assemblymethod of organic EL, FIG. 51 shows an LCD with the separation methodfor the double ion implantation layer of (D) and the assembly method oforganic EL, FIG. 52 shows an LCD with the separation method for theporous semiconductor layer and ion implantation layer of (E) and theassembly method of organic EL. Meanwhile, the term TFT substrate layermeans electrooptic display element layer in here. The following wordsare written down with abbreviations such as the surface liquid crystalassembly is abbreviated as the surface assembly, the surface singleliquid crystal assembly is abbreviated as the surface single assembly.Furthermore, it goes without saying that various other assembly methodscan be executed by applying and developing the assembly methodsmentioned above.

The LCD assembly execution example mentioned above is basically asfollows. After sealing the electrooptic display element substrate layerof the monocrystalline semiconductor substrate layer and the facingsubstrate together, the support substrate is separated from theseparation layer, the electrooptic display element substrate and thebacking or the backing chip are attached together, the liquid crystal isinjected after cutting and dividing. However, in the case of the singlesurface assembly, as required, the electrooptic display elementsubstrate layer of the monocrystalline semiconductor substrate layer andthe facing substrate are sealed together, the support substrate isseparated from the separation layer after injecting with liquid crystal,this execution example shows it is possible to have a method that is cutand divided after attaching the electrooptic display element substrateand the backing or the backing chip.

The FIG. 43 shows that the micro lens array is formed on the facingsubstrate and the transparent support substrate with high index ofrefraction material, for example the high index of refractiontransparent resin, a structure to interleave the facing substrateequipped with the micro lens which functions as the condensing lens onincident side and the transparent support substrate equipped with themicro lens which functions as the field lens of radiation side, thetransmissive type LCD for the projector with the structure generallyknown as the dual micro lens (also known as double micro lens) is shownas a execution example. However, there is no need to mention that themicro lens array can be formed with an inorganic type high index ofrefraction transparent film.

The concrete example of this execution with the example FIG. 43 is shownbelow.

With the general-purpose lithography & etching method, the micro lenssection of specified concave form is produced multiple times in thequartz glass of the facing substrate 21, neoceram substrate, etc.

The transparent glass substrate 86 of the quartz glass, neoceramsubstrate, etc. is attached with the transparent sealant 25 a afterfilling with the high index of refraction transparent resin 85 in themultiple micro lenses section. At this time, the transparent glasssubstrate 86 is attached to the facing substrate 21 with the high indexof refraction transparent resin 85, you many not need to use thetransparent sealant 25 a.

The facing substrate is equipped with the micro lens array which iscovered with the transparent glass substrate 86 (the stacked substrate)of approximately 20 μm is produced by the single sided grinding or bothside grinding.

At this time, in case of etching method, the reflective film formingsurface side of the transparent glass substrate 86 which is formed withreflective film for the black mask type such as aluminum, etc. in theregion where it is appropriate surrounding each micro lens, and thefacing substrate which is filled with high index of refractiontransparent resin inside the micro lens of specified concave form areattached together with the transparent sealant. Each micro lenssurrounding which is covered with the transparent glass substrate 86(the stacked substrate) with approximately 20 μm by single sidedgrinding or both side grinding may be produced on the facing substrateof the micro lens array formation which is shaded with the reflectivefilm of black mask action.

After producing the micro lens array in the facing substrate which iscovered with the transparent glass substrate 86 (the stacked substrate)of approximately 20 μm, the reflective film formation with a black maskaction such as aluminum, etc. can be done in the suitable region to eachmicro lens surrounding on the surface of the transparent glass substrate86 (the stacked substrate).

In other words, either the surface or the back of the transparent glasssubstrate 86 (the stacked substrate) which is suitable for thesurrounding of each micro lens can be formed with reflective film ofblack mask action.

At this time, the micro lens of the specified unevenness form may beformed multiple times on the facing substrate 21 of quartz glass,neoceram, etc. with the stamp method.

With this, the micro lens pattern of the photo resist is formed multipletimes with general purpose lithography technology, and the micro lens ofdesired convex form is formed multiple times with heating reflow.

Next, the stamper of concave form is produced by copying the type withthe resin and support stand by depositing the metallic film such asnickel with electrolysis coating on this convex form.

And, the stamper is copied to the high index of refraction transparentresin which was applied on the facing substrate, and the micro lens withconvex form is formed multiple times. A low index of refractiontransparent resin is filled in the concave section between the microlens, the transparent glass substrate such as the quartz glass orneoceram with a specified thickness, the facing substrate of the microlens array formation which is covered with the transparent glasssubstrate 86 (the stacked substrate) of approximately 20 μm may beproduced by the single sided grinding or both side grinding.

Furthermore, in the case of stamp method, the reflective film of theblack mask action of aluminum, etc. is formed on the surface of thefacing substrate which is suitable to each micro lens surrounding, thelow index of refraction transparent resin is filled in the concavesection between each micro lens, the transparent glass substrate such asthe quartz glass, neoceram, etc. with specified thickness is attached,the micro lens array formation which forms a reflective film around themicro lens which is covered with the transparent glass substrate 86 toapproximately 20 μm may be produced by the single sided grinding or bothside grinding.

In the meantime, in case of precision of the transparent glass filmthickness becomes a problem using single sided grinding or both sidegrinding, after filling the high index of refraction transparent resininside the micro lens of specified concave form, the transparent resinfilm with specified film thickness is formed with spin coating, etc.,the low reflective shielding film such as the reflective film or thechrome or chromium oxide such as aluminum with a black mask action maybe formed in the region where it is suitable around the micro lens ofthe surface of this transparent resin film.

In this way, the reflective film such as aluminum for the black maskaction is formed around the micro lens which corresponds to the displayelement region and the pixel opening section of the ultra slimelectrooptic display element substrate, at the same time, it increasesthe contrast, improves the picture quality and decreases the liquidcrystal temperature by shielding the light to the liquid crystal and byreflecting the unnecessary part of strong incident light, it isdesirable in order to have the high intensity, long life for the LCD.

A transparent electrode and alignment film 20 is formed, the micro lensarray which was equipped during the alignment process, a facingsubstrate and the pixel opening section of the display area are etched,embedded and the surface is planarized with an optically transparentmaterial 16, the transparent electrode 18 a which is connected to thedisplay element and the alignment film 20 a are formed and sealed bylaminating together with the ultra slim electrooptic display elementsubstrate layer which has completed the alignment process, after thatthe transmissive type LCD with single micro lens structure, which isinjected with liquid crystal, is produced.

The support substrate is separated from the distortion section of theporous layer or ion implantation layer under the ultra slim electroopticdisplay element substrate layer, the remainder of exfoliation is removedby chemical etching as required, and an optically transparent material16 is exposed through the SiO2 layer 13 b and the SiO2 layer 13 a.

Low reflective shielding film which is covered with transparent glasssubstrate 86 (stacked substrate) of approximately 20 μm on which isformed a low reflective light shielding film with a black mask actionwith the chrome or chromium oxide, etc. and either surface of thetransparent glass substrate 86 for example which is suitable around eachmicro lens or back, and which is manufactured the same as mentioned in3, and this ultra slim electrooptic display element substrate layer areattached together with a transparent sealant, then a transmissive typeLCD with dual micro lens structure is obtained.

At this time, by not only forming the light shielding film of the topand the side of the poly Si layer, etc. of the display element section,but also forming the black mask of the low reflective light shieldingfilm on radiation side and the reflective film on incident side of thetransparent glass substrate which is suitable around each micro lenswhere it corresponds to this display element section, you can preventthe TFT electric current leak due to strong incident light leakage ofthe projector, etc., and it is possible to achieve increased contrast,higher intensity, better picture quality and a longer life.

Until recently, the back of electrooptic display element substrate whichis laminated with the micro lens array equipped facing substrate isfinished by optical grinding and chemical etching, for example the ultraslim electrooptic display element substrate of approximately 20 um isproduced, and the micro lens array equipped on the transparent supportsubstrate are attached with the transparent sealant, and a transmissivetype LCD with dual micro lens structure is obtained. However, it wasdifficult to obtain the precision in the optical grinding and also itwas difficult to obtain the level of high intensity of the design thatwe planed and desired.

But, with each separation method of this invention, by attaching anultra slim electrooptic display element substrate layer with highlyaccurate thick film which is laminated on a facing substrate where themicro lens array formed which functions as a condensing lens, and atransparent support substrate where the micro lens array formed whichfunctions as a field lens, the transmissive type LCD for the projectorwith the dual micro lens structure which further high intensity, highdefinition and long life can be obtained because the utilizationefficiency of the emitter light can be raised by condensing theilluminant light with the double micro lens function when compared tothe former dual micro lens structure.

Furthermore, by attaching an ultra slim electrooptic display elementsubstrate layer with highly accurate thick film which is laminated on afacing substrate which forms a reflective film with black mask action inthe region where it is suitable around each micro lens which functionsas condensing lens, and a transparent support substrate of lowreflective shielding film formation with a black mask action in theregion where it is suitable around each micro lens which functions asfield lens, the transmissive type LCD for the projector of the dualmicro lens structure which has high intensity, high contrast, highdefinition and long life can be obtained because the emitter lightutilization efficiency can be raised by condensing the illuminant lightwith the double micro lens function and at the same time, unnecessaryincident light and reflective light can be removed.

FIG. 44 shows the mounted example of a transmissive type LCD for theprojector and a reflective type LCD. FIG. 44(a) is mounted example of atransmissive LCD for the projector.

The ultra slim electrooptic display element substrate layer and thefacing substrate are laminated and then the liquid crystal is injectedand sealed. After separating the support substrate, the flexible 87substrate is attached to the external output electrode 65 of the LCDpanel which consists of the ultra slim electrooptic display elementsubstrate which is attached to the transparent support substrate withtransparent sealant. And the dustproof glass 88 which is equipped withthe low reflective film on the incident side of the facing substrate isattached with the transparent sealant. After that, the dustproof glass88 which is equipped with low reflective film on the output side of thetransparent support substrate with the transparent sealant. Then, it isfixed to the aluminum metallic frame 89 which is processed with analumite blackening and with thermally conductive molding resin 90.

FIG. 44(b) is a mounted example of a reflective type LCD for theprojector. The ultra slim electrooptic display element substrate layerand the facing substrate are attached and then sealed and filled withliquid crystal. It is attached to a flexible substrate 87, to anexternal removal electrode 65 of the LCD panel which consists of theultra slim electrooptic display element substrate which attaches to themetallic support substrate with a thermally conductive and electricallyconductive sealant. And, the dustproof glass 88 which equipped lowreflective film to the facing substrate of incident side is attached. Itattaches to the aluminum metallic frame 89 which was processed withalumite and darkened, with thermally conductive mold resin 90.

In the meanwhile, at least as a dustproof glass for the incident sidefor the super slim transmissive type LCD, by attaching with atransparent sealant to the separated super thin electrooptical displayelement substrate and the transparent substrate, for example, glasswithout an antireflective film with an optical quality of rectilineartransmissivity of 80% or more and with at least 1 (W/m*K) of thermalconductivity, for instance, quartz glass and transparent crystallizedglass (neoceram, CLEARCERAM, Zerodur, etc.) etc., furthermore, glasswithout an antireflective film, and with an optical quality ofrectilinear transmissivity of 80% or more and with at least 10 (W/m*K)of thermal conductivity, for example highly transmissive ceramicpolycrystalline substances {crystalline oxides created by electromeltingor sintering of MgO (magnesia), Y₂O₃(yttrium), CaO (Calcium Oxide),AL₂O₃(Monocrystalline sapphire), BeO (beryllia), polycrystallinesapphires, etc., monocrystalline or polycrystalline of double oxidecrystalline YAG (Yttrium Aluminum Garnet), monocrystalline orpolycrystalline MgAl₂O₄(Spinel), 3Al₂O₃₂SiO₂Al₂O₃SiO₂ and so on}, afluoride monocrystalline body (calcium fluoride, magnesium fluoride andbarium fluoride etc.), vapor phase synthetic diamond film coated highlytransmissive ceramic polycrystalline substances, or a fluoridemonocrystalline body or transparent crystallized glass, or the crystaletc., this transmissive type LCD for projectors and the reflective typeLCD can achieve high intensity by promoting thermal cooling.

As an example, if the facing substrate of the thermally conductive glass(including the micro lens substrate, and the black mask substrate whichis formed on the reflective film in areas other than the pixel openingsection, etc.) which has the antireflective film formed on the incidentside, the liquid crystal, material constitution of the transparentsupport substrate of the thermally conductive glass on which was formedthe antireflective film in the ultra slim electrooptic display elementsubstrate and radiation side, or the dustproof glass of the thermallyconductive glass on which was formed the antireflective film, the facingsubstrate of thermally conductive glass (including the micro lenssubstrate, the black mask substrate on which is formed a reflective filmin areas other than the pixel opening section, etc.), the liquidcrystal, the ultra slim display element substrate, the transparentsupport substrate of thermally conductive glass and the dustproofthermally conductive glass on which is formed an antireflective film onthe radiation side, materially constitute the transmissive type LCD forthe projector in which high intensity and high definition are attainedby promoting thermal cooling.

Furthermore, for example, if the facing substrate (including the blackmask substrate) of the thermally conductive glass on which is formed anantireflective film on the incident side, the liquid crystal, the ultraslim electrooptic display element substrate, material constitution ofthe metallic support substrate, or the dustproof thermally conductiveglass on which is formed an antireflective film, the facing substratewhich is thermally conductive (including the black mask substrate) andliquid crystal materially constitute the ultra slim electrooptic displayelement substrate or metallic support substrate, and materiallyconstitute the transmissive type LCD for the projector in which highintensity and high definition is attained by promoting thermal cooling.

FIGS. 45 and 46 show examples where an ultra slim electrooptic displaydevice unit of this invention is mounted to provide a direct display.

(a) The case of an ultra slim transmissive type or semi-transmissivetype LCD for direct display.

The light diffusion plate 93 is attached to the surface of the built-inback light module 92 with transparent sealant to prevent unevenlighting.

By attaching the polarizing plate 94 to the facing substrate with thetransparent sealant directly, and attaching the ultra slim transmissiveor semi-transmissive type LCD 100 on which the polarizing plate 94 isattached to the back of transmissive backing with the transparentsealant and to the optical diffusion board. Then a transmissive orsemi-transmissive type LCD module is attached, sealing with moldingresin 95. This is connected by the bump electrode for PCB (PrintedCircuit Board) wiring 97 and the bump electrode for external outputs 98of the ultra slim typed transmissive or semi-transmissive type to thespecified position on PCB 96. After connecting the wiring 99 for backlight to the bump electrode for the wiring of PCB it is sealed withmolding resin.

(b) The case of an ultra slim reflective type LCD for direct display.

By setting the Ultra slim reflective type LCD 101 to which the directpolarization board 94 is attached to the facing substrate to thespecified position of PCB 96 with transparent sealant, it is fixed usingthe molding resin after connecting the bump electrode for externaloutputs 98 and the bump electrode for PCB wiring 97 to the PCB.

(c) The case of an ultra slim underside emitter type organic EL fordirect display.

By setting the moisture proof resin side of the ultra slim undersideemitter type organic EL102 to the specified position of PCB, it is fixedusing the molding resin after connecting the bump electrode for PCBwiring 97 and the bump electrode 98 for external outputs.

(d) The case of an ultra slim surface emitter type organic EL for directdisplay.

By setting the transmissive resin side of ultra slim surface emittertype organic EL 103 to the specified position of the PCB, it is fixedusing the molding resin after connecting the bump electrode for externaloutputs 98 and the bump electrode 97 for PCB wiring.

Furthermore, a concrete example of the ultra slim electronics productwhich uses this invention is shown in FIG. 47.

For example, in the case of a business card or a cash card type ultraslim portable telephone (audio input type), the ultra slim electroopticdisplay device unit of this invention 105, uses a reflective type LCDfor direct display, an ultra slim MOSLSi which contains the electronicsfor this invention (the DSP circuit, the CPU circuit, the image or audiomemory circuit, the image signal processing circuit, the picture qualitycompensation circuit, the audio signal processing circuit and the audiocompensation circuit, etc.) 106, the ultra slim CCD 107 and the othercomponents of this invention such as ultra slim microphone 108, theultra slim speaker 109, the antenna 110, etc. on the surface of amultiple layer PCB 104. An electric circuit with a built-in lithium ionpolymer electric battery pack 111 is mounted on the back of it. Then,connections are made between the multilayer PCB with suitable wiring andthrough the hole.

1-5. (canceled)
 6. A method of manufacturing an ultra-slim electroopticdisplay comprising: a process of forming a porous semiconductor layer ona support substrate made of a mono crystalline semiconductor, a processof forming a mono crystalline semiconductor layer via said poroussemiconductor layer on said support substrate, a process of forming aninsulating layer on a surface of said mono crystalline semiconductorlayer, and further forming an amorphous semiconductor layer or anamorphous and polycrystalline mixed semiconductor layer, or apolycrystalline semiconductor layer, a process of removing at least theamorphous semiconductor layer, the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in theperipheral circuit region while leaving the insulating layer and theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in thedisplay region, a process of forming a display device unit in theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in saiddisplay region, and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region, respectively, aprocess of separating said support substrate from said poroussemiconductor layer, a process of bonding a support on the ultra-slimelectrooptic display device substrate after said separation, and aprocess of being divided into various ultra-slim electrooptic displaysafter bonding said support.
 7. A method of manufacturing an ultra-slimelectrooptic display comprising: a process of forming a poroussemiconductor layer on a seed substrate and support substrate, each madeof a mono crystalline semiconductor, a process of forming a monocrystalline semiconductor layer on said seed substrate and supportsubstrate via said porous semiconductor layer, a process of forming aninsulating layer via said mono crystalline semiconductor layer on atleast one of said seed substrate or support substrate, a process ofbonding said seed substrate and support substrate at the surface formingsaid insulating layer, a process of separating said seed substrate fromthe porous semiconductor layer of the same seed substrate, a process offlattening the surface of said mono crystalline semiconductor layerwhich has been exposed by separating said seed substrate, by etching atleast using a hydrogen annealing treatment, a process of forming aninsulating layer on a surface of said mono crystalline semiconductorlayer, and further forming an amorphous semiconductor layer or anamorphous and polycrystalline mixed semiconductor layer, or apolycrystalline semiconductor layer, a process of removing at least theamorphous semiconductor layer, the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in theperipheral circuit region while leaving the insulating layer and theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in thedisplay region, a process of forming a display device unit in theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in saiddisplay region, and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region, a process ofseparating said support substrate from said porous semiconductor layeron the same support substrate, a process of bonding a support on theultra-slim electrooptic display device substrate after said separation,and a process of being divided into various ultra-slim electroopticdisplays after bonding said support.
 8. A method of manufacturing anultra-slim electrooptic display comprising: a process of forming aninsulating layer on a surface of a support substrate made of a monocrystalline semiconductor, and further forming an amorphoussemiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer, or a polycrystalline semiconductor layer, a processof removing at least the amorphous semiconductor layer, the amorphousand polycrystalline mixed semiconductor layer, or the polycrystallinesemiconductor layer in the peripheral circuit region while leaving theinsulating layer and the amorphous semiconductor layer or the amorphousand polycrystalline mixed semiconductor layer, or the polycrystallinesemiconductor layer in the display region, a process of forming adisplay device unit in the amorphous semiconductor layer or theamorphous and polycrystalline mixed semiconductor layer, or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, a process of forming an ion injectionlayer at a specified depth in said support substrate, a process ofperforming a separation type annealing treatment, a process ofseparating said support substrate from the strained section of said ioninjection layer, a process of bonding a support on the ultra-slimelectrooptic display device substrate after said separation, and aprocess of being divided into various ultra-slim electrooptic displaysafter bonding said support.
 9. A method of manufacturing an ultra-slimelectrooptic display comprising: a process of forming an ion injectionlayer on a seed substrate made of a mono crystalline semiconductor, aprocess of forming an insulating layer on a support substrate made of amono crystalline semiconductor, a process of forming a mono crystallinesemiconductor layer by bonding an ion injection layer of said seedsubstrate on the insulating layer of said support substrate, andsubsequently by forming a covalent bonding between said ion injectionlayer and the insulating layer with a heat treatment, a process ofseparating said seed substrate from the strained section of the ioninjection layer of the same seed substrate by performing a separationtype annealing treatment, a process of flattening by etching the surfaceof said mono crystalline semiconductor layer at least with a hydrogenannealing treatment, a process of forming an insulating layer on asurface of said mono crystalline semiconductor layer, and furtherforming an amorphous semiconductor layer or an amorphous andpolycrystalline mixed semiconductor layer, or a polycrystallinesemiconductor layer, a process of removing at least the amorphoussemiconductor layer, the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in theperipheral circuit region while leaving the insulating layer and theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in thedisplay region, a process of forming a display device unit in theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer, or the polycrystalline semiconductor layer in saiddisplay region, and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region, a process offorming an ion injection layer at a specified depth in said supportsubstrate, a process of performing a separation type annealingtreatment, a process of separating said support substrate from thestrained section of said ion injection layer, a process of bonding asupport on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support.
 10. A method ofmanufacturing an ultra-slim electrooptic display comprising: a processof forming an ion injection layer on a seed substrate made of a monocrystalline semiconductor, a process of forming a porous semiconductorlayer on a support substrate made of a mono crystalline semiconductor, aprocess of forming a mono crystalline semiconductor layer via saidporous semiconductor layer on said support substrate, a process offorming an insulating layer on said mono crystalline semiconductorlayer, a process of forming a mono crystalline semiconductor layer bybonding the ion injection layer of said seed substrate with theinsulating layer of said support substrate, and subsequently by forminga covalent bonding between said ion injection layer and the insulatinglayer using a heat treatment, a process of separating said seedsubstrate at the strained section of the ion injection layer of the sameseed substrate by performing a separation type annealing treatment, aprocess of flattening by etching the surface of said mono crystallinesemiconductor layer at least using a hydrogen annealing treatment, aprocess of forming an insulating layer on a surface of said monocrystalline semiconductor layer, and further forming an amorphoussemiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer, or a polycrystalline semiconductor layer, a processof removing at least the amorphous semiconductor layer, the amorphousand polycrystalline mixed semiconductor layer, or the polycrystallinesemiconductor layer in the peripheral circuit region while leaving theinsulating layer and the amorphous semiconductor layer or the amorphousand polycrystalline mixed semiconductor layer, or the polycrystallinesemiconductor layer in the display region, a process of forming adisplay device unit in the amorphous semiconductor layer or theamorphous and polycrystalline mixed semiconductor layer, or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, a process of separating said supportsubstrate from said porous semiconductor layer, a process of bonding asupport on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support. 11-13. (canceled) 14.A method of manufacturing an ultra-slim electrooptic display comprising:a process of forming a porous semiconductor layer both on a seedsubstrate and support substrate, each made of a mono crystallinesemiconductor, a process of forming a mono crystalline semiconductorlayer both on said seed substrate and support substrate, respectivelyvia said porous semiconductor layer, a process of forming an insulatinglayer via said mono crystalline semiconductor layer on at least one ofsaid seed substrate or support substrate, a process of bonding said seedsubstrate and support substrate at the surface forming said insulatinglayer, a process of separating said seed substrate from the poroussemiconductor layer of the same seed substrate, a process of flatteningthe surface of said mono crystalline semiconductor layer which has beenexposed by separating said seed substrate, by etching at least with ahydrogen annealing treatment, a process of exposing the insulating layerby etching the display region of said mono crystalline semiconductorlayer, a process of forming an insulating layer and an amorphoussemiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer, or a polycrystalline semiconductor layer on theentire surface, a process of forming a display device unit in theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer in saiddisplay region, and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region, wherein at leastthe amorphous semiconductor layer or the amorphous and polycrystallinemixed semiconductor layer or the polycrystalline semiconductor layerhave been etched, a process of separating said support substrate fromsaid porous semiconductor layer on the same support substrate, a processof bonding a support on the ultra-slim electrooptic display devicesubstrate after said separation, and a process of being divided intovarious ultra-slim electrooptic displays after bonding said support. 15.A method of manufacturing an ultra-slim electrooptic display comprising:a process of forming an ion injection layer on a seed substrate made ofa mono crystalline semiconductor, a process of forming an insulatinglayer on a support substrate made of a mono crystalline semiconductor, aprocess of forming a mono crystalline semiconductor layer by bonding anion injection layer of said seed substrate on the insulating layer ofsaid support substrate, and subsequently by forming a covalent bondingbetween said ion injection layer and the insulating layer with a heattreatment, a process of separating said seed substrate from the strainedsection of the ion injection layer of the same seed substrate byperforming a separation type annealing treatment, a process offlattening by etching the surface of said mono crystalline semiconductorlayer at least with a hydrogen annealing treatment, a process ofexposing the insulating layer by etching the display region of said monocrystalline semiconductor layer, a process of forming an insulatinglayer and an amorphous semiconductor layer or an amorphous andpolycrystalline mixed semiconductor layer, or a polycrystallinesemiconductor layer on the entire surface, a process of forming adisplay device unit in the amorphous semiconductor layer or theamorphous and polycrystalline mixed semiconductor layer or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, wherein at least the amorphoussemiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer have beenetched, a process of forming an ion injection layer at a specified depthin said support substrate, a process of performing a separation typeannealing treatment, a process of separating said support substrate fromthe strained section of said ion injection layer, a process of bonding asupport on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support.
 16. A method ofmanufacturing an ultra-slim electrooptic display comprising: a processof forming an ion injection layer on a seed substrate made of a monocrystalline semiconductor, a process of forming a porous semiconductorlayer on a support substrate made of a mono crystalline semiconductor, aprocess of forming a mono crystalline semiconductor layer via saidporous semiconductor layer on said support substrate, a process offorming an insulating layer on said mono crystalline semiconductorlayer, a process of forming a mono crystalline semiconductor layer bybonding the ion injection layer of said seed substrate with theinsulating layer of said support substrate, and subsequently by forminga covalent bonding between said ion injection layer and the insulatinglayer using a heat treatment, a process of separating said seedsubstrate at the strained section of the ion injection layer of the sameseed substrate by performing a separation type annealing treatment, aprocess of flattening by etching the surface of said mono crystallinesemiconductor layer at least using a hydrogen annealing treatment, aprocess of exposing the insulating layer by etching the display regionof said mono crystalline semiconductor layer, a process of forming aninsulating layer and an amorphous semiconductor layer or an amorphousand polycrystalline mixed semiconductor layer, or a polycrystallinesemiconductor layer on the entire surface, a process of forming adisplay device unit in the amorphous semiconductor layer or theamorphous and polycrystalline mixed semiconductor layer or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, wherein at least the amorphoussemiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer have beenetched, a process of separating said support substrate from said poroussemiconductor layer on the same support substrate, a process of bondinga support on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support. 17-19. (canceled) 20.A method of manufacturing an ultra-slim electrooptic display comprising:a process of forming a porous semiconductor layer both on a seedsubstrate and support substrate, each made of a mono crystallinesemiconductor, a process of forming a mono crystalline semiconductorlayer both on said seed substrate and support substrate, respectivelyvia said porous semiconductor layer, a process of forming an insulatinglayer via said mono crystalline semiconductor layer on at least one ofsaid seed substrate or support substrate, a process of bonding said seedsubstrate and support substrate at the surface forming said insulatinglayer, a process of separating said seed substrate from the poroussemiconductor layer of the same seed substrate, a process of flatteningthe surface of said mono crystalline semiconductor layer which has beenexposed by separating said seed substrate, by etching at least with ahydrogen annealing treatment, a process of exposing the insulating layerby etching the display region of said mono crystalline semiconductorlayer, a process of forming a light-shielding metallic layer in theamorphous semiconductor layer or amorphous and polycrystalline mixedsemiconductor layer or polycrystalline semiconductor display deviceforming region of the display region, a process of forming an insulatinglayer and an amorphous semiconductor layer or an amorphous andpolycrystalline mixed semiconductor layer, or a polycrystallinesemiconductor layer on the entire surface, a process of forming adisplay device unit in the amorphous semiconductor layer or theamorphous and polycrystalline mixed semiconductor layer or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, wherein at least the amorphoussemiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer have beenetched, a process of separating said support substrate from said poroussemiconductor layer on the same support substrate, a process of bondinga support on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support.
 21. A method ofmanufacturing an ultra-slim electrooptic display comprising: a processof forming an ion injection layer on a seed substrate made of a monocrystalline semiconductor, a process of forming an insulating layer on asupport substrate made of a mono crystalline semiconductor, a process offorming a mono crystalline semiconductor layer by bonding an ioninjection layer of said seed substrate on the insulating layer of saidsupport substrate, and subsequently by forming a covalent bondingbetween said ion injection layer and the insulating layer with a heattreatment, a process of separating said seed substrate from the strainedsection of the ion injection layer of the same seed substrate byperforming a separation type annealing treatment, a process offlattening by etching the surface of said mono crystalline semiconductorlayer at least with a hydrogen annealing treatment, a process ofexposing the insulating layer by etching the display region of said monocrystalline semiconductor layer, a process of forming a light-shieldingmetallic layer in the amorphous semiconductor layer or amorphous andpolycrystalline mixed semiconductor layer or polycrystallinesemiconductor display device forming region of the display region, aprocess of forming an insulating layer and an amorphous semiconductorlayer or an amorphous and polycrystalline mixed semiconductor layer, ora polycrystalline semiconductor layer on the entire surface, a processof forming a display device unit in the amorphous semiconductor layer orthe amorphous and polycrystalline mixed semiconductor layer or thepolycrystalline semiconductor layer in said display region, and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region, wherein at least the amorphoussemiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer have beenetched, a process of forming an ion injection layer at a specified depthin said support substrate, a process of performing a separation typeannealing treatment, a process of separating said support substrate fromthe strained section of said ion injection layer, a process of bonding asupport on the ultra-slim electrooptic display device substrate aftersaid separation, and a process of being divided into various ultra-slimelectrooptic displays after bonding said support.
 22. A method ofmanufacturing an ultra-slim electrooptic display comprising: a processof forming an ion injection layer on a seed substrate made of a monocrystalline semiconductor, a process of forming a porous semiconductorlayer on a support substrate made of a mono crystalline semiconductor, aprocess of forming a mono crystalline semiconductor layer via saidporous semiconductor layer on said support substrate, a process offorming an insulating layer on said mono crystalline semiconductorlayer, a process of forming a mono crystalline semiconductor layer bybonding the ion injection layer of said seed substrate with theinsulating layer of said support substrate, and subsequently by forminga covalent bonding between said ion injection layer and the insulatinglayer using a heat treatment, a process of separating said seedsubstrate at the strained section of the ion injection layer of the sameseed substrate by performing a separation type annealing treatment, aprocess of flattening by etching the surface of said mono crystallinesemiconductor layer at least using a hydrogen annealing treatment, aprocess of exposing the insulating layer by etching the display regionof said mono crystalline semiconductor layer, a process of forming alight-shielding metallic layer in the amorphous semiconductor layer oramorphous and polycrystalline mixed semiconductor layer orpolycrystalline semiconductor display device forming region of thedisplay region, a process of forming an insulating layer and anamorphous semiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer, or a polycrystalline semiconductor layer on theentire surface, a process of forming a display device unit in theamorphous semiconductor layer or the amorphous and polycrystalline mixedsemiconductor layer or the polycrystalline semiconductor layer in saiddisplay region, and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region, wherein at leastthe amorphous semiconductor layer or the amorphous and polycrystallinemixed semiconductor layer or the polycrystalline semiconductor layerhave been etched, a process of separating said support substrate fromsaid porous semiconductor layer, a process of bonding a support on theultra-slim electrooptic display device substrate after said separation,and a process of being divided into various ultra-slim electroopticdisplays after bonding said support.
 23. (canceled)
 24. The method ofmanufacturing an ultra-slim electrooptic display as claimed in claim 6,including a process of forming a polycrystalline semiconductor layerwith controlled crystal grain size by solid phase crystallization afterselective ion injection or ion doping using at least one kind of GroupIV elements for an amorphous semiconductor layer or an amorphous andpolycrystalline mixed semiconductor layer or a polycrystallinesemiconductor layer in said display region, and a process of forming adisplay device unit in the polycrystalline semiconductor layer havingthe controlled crystal grain size in said display region and aperipheral circuit unit in the mono crystalline semiconductor layer ofsaid peripheral circuit region.
 25. (canceled)
 26. The method ofmanufacturing an ultra-slim electrooptic display as claimed in claim 6,including a process of forming a polycrystalline semiconductor layerwith controlled crystal grain size after recrystallization of anamorphous semiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer or a polycrystalline semiconductor layer in saiddisplay region, and a process of forming a display device unit in thepolycrystalline semiconductor layer having the controlled crystal grainsize in said display region and a peripheral circuit unit in the monocrystalline semiconductor layer of said peripheral circuit region. 27.(canceled)
 28. The method of manufacturing an ultra-slim electroopticdisplay as claimed in claim 6, including a process of forming apolycrystalline semiconductor layer with controlled crystal grain sizeby recrystallization after selective ion injection or ion doping usingat least one kind of Group IV elements for an amorphous semiconductorlayer or an amorphous and polycrystalline mixed semiconductor layer or apolycrystalline semiconductor layer in said display region, and aprocess of forming a display device unit in the polycrystallinesemiconductor layer having the controlled crystal grain size in saiddisplay region and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region. 29-30. (canceled)31. The method of manufacturing an ultra-slim electrooptic display asclaimed in claim 6, including a process of forming for an amorphoussemiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer or a polycrystalline semiconductor layer containingat least one kind of Group IV elements in said display region and a monocrystalline semiconductor layer in said peripheral circuit region, aprocess of forming a polycrystalline semiconductor layer with controlledcrystal grain size by solid phase crystallization selectively for anamorphous semiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer or a polycrystalline semiconductor layer in saiddisplay region, and a process of forming a display device unit in thepolycrystalline semiconductor layer having the controlled crystal grainsize in said display region and a peripheral circuit unit in the monocrystalline semiconductor layer of said peripheral circuit region. 32.The method of manufacturing an ultra-slim electrooptic display asclaimed in claim 6, including a process of forming for an amorphoussemiconductor layer or an amorphous and polycrystalline mixedsemiconductor layer or a polycrystalline semiconductor layer containingat least one kind of Group IV elements in said display region and a monocrystalline semiconductor layer in said peripheral circuit region, aprocess of forming a polycrystalline semiconductor layer with controlledcrystal grain size by recrystallization for an amorphous semiconductorlayer or an amorphous and polycrystalline mixed semiconductor layer or apolycrystalline semiconductor layer in said display region, and aprocess of forming a display device unit in the polycrystallinesemiconductor layer having the controlled crystal grain size in saiddisplay region and a peripheral circuit unit in the mono crystallinesemiconductor layer of said peripheral circuit region. 33-37. (canceled)